IMX27L datasheet(82/122 Pages) FREESCALE

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i.MX27/iMX27L Data Sheet, Advance Information, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

Signal Descriptions

Figure 42. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram

NOTE

SDRAM CLK and DQS related parameters are being measured from the

50% point—that is, high is defined as 50% of signal value and low is

defined as 50% of signal value.

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 41 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

3.6.9.1

SDHC Electrical DC Characteristics

Table 42 lists the SDHC electrical DC characteristics.

Table 41. Mobile DDR SDRAM Read Cycle Timing Parameters

Parameter

Symbol

Min

Max

Unit

SD21

DQS–DQ Skew (defines the Data valid window in read cycles related to DQS).

tDQSQ

—

0.85

SD22

DQS DQ HOLD time from DQS

tQH

2.3

—

SD23

DQS output access time from SDCLK posedge

tDQSCK

—

6.7

Table 42. SDHC Electrical DC Characteristics

Parameter

Min

Max

Unit

Comments

General

SD10

Peak Voltage on All Lines

–0.3

VDD + 0.3

—

All Inputs

SD11

Input Leakage Current

–10

μA—

All Outputs

SD12

Output Leakage Current

–10

μA—

Power Supply

SDCLK

DQS (input)

DQ (input)

Data

SD23

SD21

SD22

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