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IMX27L Datasheet(PDF) 89 Page - Freescale Semiconductor, Inc |
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IMX27L Datasheet(HTML) 89 Page - Freescale Semiconductor, Inc |
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89 / 122 page ![]() Signal Descriptions i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 89 Figure 48. SSI Receiver with Internal Clock Timing Diagram Table 46. SSI Receiver with Internal Clock Timing Parameters ID Parameter Min Max Unit Internal Clock Operation SS1 (Tx/Rx) CK clock period 81.4 — ns SS2 (Tx/Rx) CK clock high period 36.0 — ns SS3 (Tx/Rx) CK clock rise time — 6 ns SS4 (Tx/Rx) CK clock low period 36.0 — ns SS5 (Tx/Rx) CK clock fall time — 6 ns SS7 (Rx) CK high to FS (bl) high — 15.0 ns SS9 (Rx) CK high to FS (bl) low — 15.0 ns SS11 (Rx) CK high to FS (wl) high — 15.0 ns SS13 (Rx) CK high to FS (wl) low — 15.0 ns SS20 SRXD setup time before (Rx) CK low 10.0 — ns SS21 SRXD hold time after (Rx) CK low 0 — ns Oversampling Clock Operation SS47 Oversampling clock period 15.04 — ns SS50 SS48 DAM1_T_CLK DAM1_T_FS (bl) DAM1_T_FS (wl) DAM1_RXD DAM1_R_CLK SS3 SS1 SS4 SS2 SS5 SS51 SS20 SS21 SS49 SS7 SS9 SS11 SS13 SS47 (Output) (Output) (Output) (Input) (Output) |
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