4518 datasheet(27/160 Pages) RENESAS

27 / 160 page

Rev.3.01

2005.06.15

page 27 of 157

REJ03B0008-0301

4518 Group

(3) External interrupt control registers

• Interrupt control register I1

rupt. Set the contents of this register through register A with the

TI1A instruction. The TAI1 instruction can be used to transfer the

contents of register I1 to register A.

Table 8 External interrupt control register

• Interrupt control register I2

rupt. Set the contents of this register through register A with the

TI2A instruction. The TAI2 instruction can be used to transfer the

contents of register I2 to register A.

I13

I12

I11

I10

INT0 pin input control bit

Interrupt valid waveform for INT0 pin/

return level selection bit

INT0 pin edge detection circuit control bit

INT0 pin Timer 1 count start synchronous

circuit selection bit

Interrupt control register I1

R/W

TAI1/TI1A

at RAM back-up : state retained

at reset : 00002

INT0 pin input disabled

INT0 pin input enabled

Falling waveform/“L” level (“L” level is recognized with the SNZI0

instruction)

Rising waveform/“H” level (“H” level is recognized with the SNZI0

instruction)

One-sided edge detected

Both edges detected

Timer 1 count start synchronous circuit not selected

Timer 1 count start synchronous circuit selected

I23

I22

I21

I20

INT1 pin input control bit (Note 2)

Interrupt valid waveform for INT1 pin/

return level selection bit (Note 2)

INT1 pin edge detection circuit control bit

INT1 pin Timer 3 count start synchronous

circuit selection bit

Interrupt control register I2

R/W

TAI2/TI2A

at RAM back-up : state retained

at reset : 00002

INT1 pin input disabled

INT1 pin input enabled

Falling waveform/“L” level (“L” level is recognized with the SNZI1

instruction)

Rising waveform/“H” level (“H” level is recognized with the SNZI1

instruction)

One-sided edge detected

Both edges detected

Timer 3 count start synchronous circuit not selected

Timer 3 count start synchronous circuit selected

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set.

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