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4518 Datasheet(PDF) 33 Page - Renesas Technology Corp |
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4518 Datasheet(HTML) 33 Page - Renesas Technology Corp |
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33 / 160 page  Rev.3.01 2005.06.15 page 33 of 157 REJ03B0008-0301 4518 Group Fig. 26 Timer structure (2) 1 - - - - - - - - - - - - - - 16 Watchdog timer INSTCK Q R S WDF1 WRST instruction Q R S WEF DWDT instruction + WRST instruction RESET signal Q T D R RESET signal Watchdog reset signal PWMOUT 0 1 I22 0 1 P31/INT1 W33 T3UDF I20 I23 I21 W31, W30 10 11 01 00 ORCLK T2UDF T3F (TAB3) (TAB3) (T3AB) (T3AB) (T3AB) Timer 3 (8) Timer 3 interrupt Reload register R3 (8) Register B Register A Timer 3 underflow signal (T3UDF) One-sided edge detection circuit Both edges detection circuit W32 1 0 W63 0 1 I20 S R Q 1 0 W43 PWMOD Q R D T W32 W61 T3UDF Port D7 output D7/CNTR1 Register B Register A Reload register R4H (8) (TAB4) (TAB4) (T4AB) (T4AB) (T4AB) Timer 4 (8) Reload register R4L (8) Register B Register A Reload control circuit W41 1 0 W40 1/2 ORCLK XIN “H” interval expansion 0 1 W42 T4F R Q T W43 PWMOUT (T4HAB) (T4R4L) Timer 4 interrupt (Note 4) (TR3AB) (Note 3) (Note 5) (Note 6) TR3AB: T4R4L: INSTCK: ORCLK: This instruction is used to transfer the contents of register A and register B to only reload register R3. This instruction is used to transfer the contents of reload register R4L to timer 4. Instruction clock (system clock divided by 3) Prescaler output (instruction clock divided by 1 to 256) Data is set automatically from each reload register when timer underflows (auto-reload function). Notes 3: XIN cannot be used for the count source when bit 1 (MR1) of register MR is set to “1” and f(XIN) oscillation is stopped. 4: Timer 3 count start synchronous circuit is set by the valid edge of P31/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2. 5: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = “1”. The next instruction is not skipped even when the WRST instruction is executed while flag WDF1 = “0”. 6: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 7: The WEF flag is set to “1” at system reset or RAM back-up mode. (Note 7) |
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