M37160MF datasheet(111/131 Pages) RENESAS

111 / 131 page

Rev.1.01

2003.11.13

page 111 of 130

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP

b7 b6 b5 b4 b3 b2 b1 b0

Block control register i (BCi) (i=1, 2) [Addresses 00D216 and 00D316]

Block Control register i

0, 1 Display mode

selection bits

(BCi0, BCi1)

(See note 4)

Indeterminate

2, 3 Dot size selection

bits (BCi2, BCi3)

b2 Pre-divide Ratio

Dot Size

Pre-divide ratio

selection bit (BCi4)

Window top/bottom

boundary control bit

(BCi7)

Notes 1:Tc is OSD clock cycle divided in pre-divide circuit.

2:H is HSYNC.

Vertical display start

position control bit

(BCi6)

BC16: Block 1

BC26: Block 1

b1 b0

0 0: Display OFF

0 1: OSD1 mode

1 0: OSD2 mode (Border OFF)

1 1: OSD2 mode (Border ON)

/CD OSD mode (Border OFF)

✕ 2

✕ 3

1Tc ✕ 1/2H

1Tc ✕ 1H

2Tc ✕ 2H

3Tc ✕ 3H

1Tc ✕ 1/2H

1Tc ✕ 1H

2Tc ✕ 2H

3Tc ✕ 3H

BC17: Window top boundary

BC27: Window bottom boundary

Name

Functions

After reset

Indeterminate RW

0: 2 value output control

1: 3 value output control

(See note 3)

3: Refer to the corresponding figure 8.10.18.

OUToutput control bit

(BCi5)

(See note 1)

4: Selection in OSD2 mode/CD OSD mode is performed in the bits 0 and 1

of color dot OSD control registration.

Address 00D116

Address 00D216, 00D316

b7 b6 b5 b4 b3 b2 b1 b0

Horizontal position register (HP) [Address 00D116]

Name

Horizontal Position Register

Horizontal display start

position control bits

(HP0 to HP6)

Nothing is assigned. This bit is a write disable bit.

When this bit is read out, the value is “0.”

Functions

After reset R W

Horizontal display start position

4Tosc ✕ n

(n: setting value, Tosc: OSD oscillation cycle)

R —

Note: The setting value synchronizes with the V SYNC.

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