M37160MF datasheet(122/131 Pages) RENESAS

122 / 131 page

Rev.1.01

2003.11.13

page 122 of 130

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt request register 1 (IREQ1) [Address 00FC16]

Interrupt Request Register 1

Name

Functions

Afrer reset

0 : No interrupt request issued

1 : Interrupt request issued

Timer 1 interrupt request

bit (TM1R)

Timer 2 interrupt request

bit (TM2R)

Timer 3 interrupt request

bit (TM3R)

Timer 4 interrupt request

bit (TM4R)

OSD interrupt

request bit (OSDR)

VSYNC interrupt request

bit (VSCR)

INT3 external interrupt

request bit (IN3R)

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

✽: “0” can be set by software, but “1” cannot be set.

—

✽

Nothing is assigned. This bit is a write disable bit.

When this bit is read out, the value is “0.”

b7 b6 b5 b4 b3 b2 b1 b0

After reset RW

CPU Mode Register

0, 1

3, 4

Name

Functions

Processor mode bits

(CM0, CM1)

0 0: Single-chip mode

0 1:

1 0:

Not available

1 1:

Fix these bits to “1.”

Stack page selection

bit (CM2) (See note1)

b1 b0

0: 0 page

1: 1 page

Main Clock (XIN) stop bit

(CM6)

CPU mode register (CM) [Address 00FB16]

R W

XCOUT drivability

selection bit (CM5)

0: LOW drive

1: HIGH drive

0: Oscillating

1: Stopped

Internal system clock

selection bit

(CM7) (See note2)

0: XIN selected

(high-speed mode)

1: XCIN–XCOUT selected

or FSCIN input selected

(low-speed mode)

Note 1: This bit is set to “1” after the reset release.

2: XCIN-XCOUT and FSCIN are switched over using Clock

Control Register 2 (address 021116) bit 2.

Address 00FB16

Address 00FC16

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