M66290AFP datasheet(34/54 Pages) RENESAS

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USB DEVICE CONTROLLER

M66290AGP/FP

MITSUBISHI <DIGITAL ASSP>

Reset

Name

Bit

0000

W/R

Write/Read "0"

Appoint the CPU access endpoint.

"0001"=EP1,"0010"=EP2,"0011"=EP3,

"0100"=EP4,"0101"=EP5

EP0 can not be appointed.

Don't change the setting in writing (IN) or in reading (OUT).

Change of the setting of the endpoint of direction IN must be

done after confirmed that IVAL="0" and Creq="0", or IVAL="1"

and Creq="1".

Change of the setting of the endpoint of direction OUT must

be done after confirmed that IVAL="1" and Creq="0", or

IVAL="0" and Creq="1".

CPU access

endpoint

RCNT

If this bit is "1", every time when read CPU_FIFO register,

CPU_DTLN register value is counted down.

Read count mode

CPU_EP

[3:0]

Reserved

14 to 4

3 to 0

Bit

Name

Function

W/R

USB

S/W

H/W

CPU_EP[3:0]

RCNT

D10

D11

D12

D15

D13

D14

(4-1) CPU_FIFO Selection Register (Address : 40h)

Function

Bit

Name

W/R

Write/Read "0"

If the selected endpoint is set to IN, this becomes IN buffer

effective state flag.

When set to "1", it becomes transmit data set state.

(SIE is available to read)

When the data (byte) which exceeds to the maximum packet size

(MXPS) is written, this bit is set to "1".

In short packet transmit, set this bit to "1" after wrote the transmit data.

If IVAL="1" and BCLR="1" is written at the same time, the

effective state flag is set.

(This is effective to transmit 0 length data)

If the selected endpoint is set to OUT, it becomes to

OUT buffer effective state status.

Status "1" shows that there is data which is available to read.

When Creq bit is "0", this bit shows effective value.

This bit is not changed when "1" is written.

Flag is not changed when "0" is written.

IN buffer status

IVAL

Reserved

15, 14

Bit

Name

W/R

USB

S/W

H/W

Reset

CPU_DTLN[10:0]

Creq

BCLR

IVAL

D10

D11

D12

D15

D13

D14

(4-2) CPU_FIFO Control Register (Address : 42h)

M66290AFP Datasheet(PDF) 34 Page - Renesas Technology Corp

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