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M66290AFP Datasheet(PDF) 27 Page - Renesas Technology Corp

Part # M66290AFP
Description  USB DEVICE CONTROLLER
PDF  54 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M66290AFP Datasheet(HTML) 27 Page - Renesas Technology Corp

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USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
26
Reset
Name
Bit
Write/Read "0"
-
-
0
W/R
-
-
0
W/R
When "1" is written into this bit, automatic response mode of
Set_Address request is set.
To the Set_Address request in automatic response mode,
transfer can be completed without occurring the interrupt to
CPU. (Set of CCPL is not needed)
Automatic response is done to the Set_Address request (DeviceAddress
is equal to 01h to 7Fh) which device state is Default state.
To the other state and to the Set_Address request which DeviceAddress
is not equal to 01h to 7Fh, automatic response is not done.
When "1" is written into this bit, auto-response mode of
Set_Configuration request is set.
To the Set_Configuration request in auto-response mode,
transfer can be completed without occurring interrupt to CPU.
(Set of CCPL is not needed)
Auto-response is done to the Set_Configuration request
(ConfigurationValue is not equal to 0) in Address device state
and to the Set_Configuration request (ConfigurationValue is equal to 0)
in Configured state.
To the other state and to the Set_Configuration request which
ConfigurationVale is different from the value above, auto-response
is not done.
Set_Address
Auto-response
mode
Set_Configuration
Auto-response
mode
ASTD
ASCN
0
1
15 to 2 Reserved
Bit
Name
Function
W/R
USB
S/W
H/W
ATAD
ASCN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D15
D13
D14
(3-7) Auto-response Control Register (Address : 2Ch)
Function
Bit
Name
-
-
0
W/R
-
-
0
W/R
-
-
0
W/R
Write/Read "0"
Write/Read "0"
0 : Control write (OUT) buffer select
1 : Control read (IN) buffer select
Buffer select
If this bit is "1", every time when read EP0_FIFO register,the value of
ODLN register is counted down.
Read count mode
If this bit is set to "1", data register of FIFO turns to 8-bit mode and
lower 8 bit[7:0] becomes enable when access the "FIFO Data Register"
of endpoint.
When transmit data of odd number byte, data must be written in 8-bit
mode.
When read in 8-bit mode, set to 8-bit mode before data receive.
FIFO access
8 bit mode
ISEL
Reserved
9-1
Octl
10
Reserved
RCNT
14 to 11
15
0
Bit
Name
W/R
USB
S/W
H/W
Reset
Octl
RCNT
ISEL
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D15
D13
D14
(3-8) EP0_FIFO Selection Register (Address : 30h)



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