M66290AFP datasheet(17/54 Pages) RENESAS

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USB DEVICE CONTROLLER

M66290AGP/FP

MITSUBISHI <DIGITAL ASSP>

Bit

Name

Function

Reset

This bit changes to "1" at the timing of token packet receive end when

buffer respond NAK, of its not ready state, to IN/OUT token of each

endpoint.

The endpoint which occurred the interrupt is checked to see

EPB_NRDY[5:0].

This flag is cleared to clear the status flag of EPB_NRDY[5:0].

Endpoint5-0 buffer

not ready

interrupt enable

INTN

This bit changes to "1" when the buffer of each endpoint

became ready (read/write enable).

The endpoint which occurred the interrupt is checked to see

EPB_RDY[5:0].

This flag is cleared to clear the status flag of

EPB_RDY[5:0].

Endpoint5-0 buffer

ready

interrupt enable

INTR

W/R

000

001

000

Ext.

000: Powered State

001: Default State

010: Address State

011: Configured State

1xx: Suspended State

Device state can be known.

As to the device state shift, refer to Fig.5 in the later part.

When detect USB reset, this becomes 001: Default state automatically.

When detect suspend, this becomes 1xx: Suspended state automatically.

Whatever the automatic response mode is, this becomes 010: Address

state after executed Set_Address request, and becomes 011: Configured

state after executed Set_Configuration request.

(Write operation is available when S/W control mode is set)

Device state

This bit changes to "1" when received setup packet.

This flag does not the factor of interrupt.

When "0" is written, status flag is cleared .

When "1" is written, flag is not changed .

Setup packet

detect

000 : Idle or Setup stage

001 : Control read transfer data stage

010 : Control read transfer status stage

011 : Control write transfer data stage

100 : Control write transfer status stage

101 : Control write no data transfer status stage

110 : Control transfer sequence error

111 : Not assigned

Can be seen the stage of control transfer.

As to the stage shift of control transfer, refer to Fig.5 in the later part.

(Write operation is available when S/W control mode is set)

Control transfer

Stage

2-0

Vbus input port

Input data from external Vbus is stored.

0: Vbus input port is "L"

1: Vbus input port is "H"

External Vbus input data is latched by the positive edge of internal clock.

Refer to this bit after enabled internal clock operation.

DVSQ

[2:0]

6-4

CTSQ

[2:0]

VALID

Vbus

W/R

USB

S/W

H/W

M66290AFP Datasheet(PDF) 17 Page - Renesas Technology Corp

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