M66290AFP datasheet(31/54 Pages) RENESAS

31 / 54 page

USB DEVICE CONTROLLER

M66290AGP/FP

MITSUBISHI <DIGITAL ASSP>

FIFO control

Access to endpoint buff er of EP0 to EP5 is done by

three FIFO data registers. One is only f or EP0 and

Others are common to EP1 to EP5. Common data

registers are div ided into two, because accessing

is diff erent, that is f or CPU access and f or DMA

transf er. Which endpoint of EP1 to EP5 to be

accessed can be selected to set each FIFO

selection register.

Endpoint

EP0

EP1 to EP5

Accessing

CPU access

DMA transf er

EP0_FIFO

data register

CPU_FIFO

data register

DMA_FIFO

data register

Each of three FIFO registers has f unctions as

f ollows. And these f unctions can be used to set

"Each FIFO Selection/Control Register".

Short packet transmission f unction

(IVAL : IN buff er status bit)

Transmit/receiv e buff er clear f unction

(BCLR : Buff er clear bit)

Null data (data length 0) transmit f unction

(IVAL & BCLR)

Data length (8/16 bit) set f unction

(Octl : Register 8bit mode bit)

Receiv ed data length count down f unction

(RCNT : Read count mode bit)

*: There is none f or DMA transf er

Access to CPU_FIFO data register when interrupt

occurred, to know the endpoint which requested

access, access the "Interrupt Status Register 0/1"

and by checking the interrupt status f lag and know

the endpoint which requested access, and then set

endpoint to be accessed by "CPU_FIFO Selection

If there is no change of endpoint setting, it is not

needed to set again the CPU access endpoint

appointment bit.

Data transfer procedure

Data which is set to endpoint FIFO, is sent to USB

bus by LSB f irst. When store the receiv ed data

f rom USB bus to endpoint FIFO, it is as the same

as abov e.

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14D15

Time scale

(Data send procedure to USB bus)

DMA transfer

To endpoint of EP1 to EP5, 16bits width or 8bit width of

DMA

transf er is av ailable.

Each endpoint of EP1 to EP5 can be set to CPU access

mode or DMA access mode by set of "EPx Conf iguration

DMA transf er is realized to hand shake with external DMAC

and Dreq, Dack signal. Dreq is asserted when endpoint

buff er, which is set to DMA transf er mode, became ready.

The means of Buff er ready state is, if the endpoint

transf er

direction is set to Out (reciv e data f rom host) buff er ready

means that in read enable state, if the endpoint transf er

direction is set to IN(transmit data to host) buff er ready

means that in write enable state. Setting the transf er

direction can be done by "EPi Conf iguration Register 0" to

each endpoint.

When Dack comes f rom external DMAC af ter asserted

Dreq, Dreq is negated.

In DMA transf er, Dack is dealt equiv alently with CS signal

and DMA_FIFO address appointment.

Appoint read or write operation by RD or WR signal.

This DMA transf er can be used only f or single transf er,

which

transf ers one word (16bit or 8bit) by one time Dreq start.

In DMA transf er, as same as the CPU access, occurs

endpoint buff er not ready interrupt and endpoint buff er

empty interrupt according to endpoint buff er state. But as

to endpoint buff er ready interrupt, it is not same as the

CPU access as f ollows.

In DMA transf er, endpoint buff er ready interrupt is not

occurred if the transf er direction is IN.

If the transf er direction is OUT, interrupt is occurred when

receiv ed short data packet and ended data transf er of all

data which receiv ed in DMA transf er.

Occurring of endpoint buff er ready interrupt and to ref er

DMA_DTLN, it can be known that short data packet was

receiv ed.

DMA_DTLN shows the number of by te of short data

packet,

or in the continuous receiv e mode it shows the number of

by te

of receiv ed data bef ore short data packet receiv e.

M66290AFP Datasheet(PDF) 31 Page - Renesas Technology Corp

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