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M66290AFP Datasheet(PDF) 36 Page - Renesas Technology Corp |
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M66290AFP Datasheet(HTML) 36 Page - Renesas Technology Corp |
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36 / 54 page  USB DEVICE CONTROLLER M66290AGP/FP MITSUBISHI <DIGITAL ASSP> 35 - - xxxx W/R If the selected endpoint is set to OUT, this becomes to receive data FIFO register. If the selected endpoint is set to IN, this becomes to transmit data FIFO register. If the selected endpoint is set to 8-bit mode, lower 8 bit [7:0] is valid. When read or write, 200ns (min) of cycle time is needed. (Continuous access at 5MHz is available) Read operation when direction IN is appointed or write operation when direction OUT is appointed, write operation is inhibited. CPU_FIFO data CPU_FIFO [15:0] 15 to 0 Bit Bit Name Name Function W/R USB S/W H/W Reset - - 0 W/R Set the operation mode of DMA transfer. 0 : High speed transfer mode 1 : One word transfer mode In high speed transfer mode, when endpoint buffer is in read/write enable in the state that DMA transfer enable, Dreq is asserted. In one word transfer mode, when endpoint buffer is in read/write enable in the state that DMA transfer enable and Dack="H", Dreq is asserted. In both mode, Dreq detects Dack="L" and is negated. DMA operation mode MODE 15 Reset Function Name Bit Name Bit Write/Read "0" Reserved 14 to 9 - - 0 W/R - - 0000 W/R Write/Read "0" Appoint the endpoint for DMA transfer. "0001"=EP1,"0010"=EP2,"0011"=EP3, "0100"=EP4,"0101"=EP5 EP0 can not be appointed. Don't change the setting during write (IN) or read (OUT). Change of the setting of the endpoint of direction IN must be done after confirmed that IVAL="0" and Dreq="0", or IVAL="1" and Dreq="1". Change of the setting of the endpoint of direction OUT must be done after confirmed that IVAL="0" and Dreq="1". DMA transfer endpoint If this bit is "1", endpoint buffer which is appointed by DMA_EP[3:0] is enable to write or when read is enable, Dreq is asserted. If "0" is written in DMA transferring, DMA transfer is forced to end. DMA transfer enable Reserved DMA_EP [3:0] 3 to 0 7 to 4 DMAEN 8 W/R USB S/W H/W MODE DMAEN DMA_EP[3:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D15 D13 D14 (4-3) CPU_FIFO Data Register (Address : 44h) (4-4) DMA_FIFO Selection Register (Address : 48h) CPU_FIFO[15:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D15 D13 D14 |
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