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M66290AFP Datasheet(PDF) 7 Page - Renesas Technology Corp |
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M66290AFP Datasheet(HTML) 7 Page - Renesas Technology Corp |
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7 / 54 page ![]() USB DEVICE CONTROLLER M66290AGP/FP MITSUBISHI <DIGITAL ASSP> 6 Functional and register descriptions We explain about Function and register constitution of M66290A div iding into f our items as f ollows. (1) Sy stem control (2) Interrupts (3) Control transf er/enumeration (4) Endpoints and FIFO control (1) System control CLOCK Clock of 48MHz is needed f or internal operations of M66290A. Built in PLL enables to input external clock of 6/12/ 24/48MHz. Selection of it is realized by the XTAL of "USB Operation Enable Register". When use external clock of 48MHz, PLL is not needed, so set to PLL operation disable. Built in oscillation circuit enables to supply clock by self oscillation. RESET S/W reset by the register set (USBE), diff erent f rom the hardware reset, keeps the v alue of register of USB operation enable register, FIFO relational register, control transf er relational register,endpoint setting register, and so on. And in USB reset (when more than 2.5us of SE0 state is continued on D+, D- terminal), the v alue of register is kept except f or "Interrupt Status Register 0" and "USB_Address Register" As to details of reset state, see each item of register. D+ pull-up resistor control f unction To set the register, external TrON output is controlled and can control the ON/OFF of pull-up resistor (1.5kohm) on USB D+ line. And when use this f unction, dev ice state shif ts to Address state af ter outputs remote wakeup signal, so it is needed to set up again the dev ice state to Conf igured state. Change of set up of dev ice state can be done in S/W control mode. Remote wakeup signal is a signal to set USB bus to idle state af ter output K-state of 10ms length. If this remote wakeup f unction is set up immediately af ter detected suspend, USB bus idle state is kept f or 2ms and then shif ts to K state output. (Because USB bus idle state must be kept f or 5ms minimum until transmit of remote wakeup signal, on the other hand af ter detect suspend, USB idle state is continued f or 3ms) Sequence toggle bit clear f unction In each endpoint of EP0 to EP5, data PID can be reset independently and also can appoint PID of DATA0. By this f unction, management of sequence toggle bit in transf er af ter reset PID, is done by H/W automatically. Error inf ormation in isochronous transf er In isochronous transf er there is not retry f unction of transmit/receiv e, because the handshake f rom receiv er to transmitter is not returned not to disturb the time equiv alent data transf er. M66290A has enough inf ormation f unction which enables f irmware to manage incorrect transf er in case of transf er error occurred in isochronous transf er. Inf ormation which M66290A can inf orm is, ov er run error, under run error, receiv ed data error (CRC error, bit stuff ing error), and f rame number. Sof tware control mode In sof tware control mode, it is av ailable to set up (write) f rom CPU as f ollows, USB_Address register (USB_Addr), dev ice state register (DVSQ), control transf er stage register (CTSQ). Normally , use this mode with OFF. To set the "USB Operation Enable Register", it can be set the dev ice to standby state. Oscillation is halted (clock input halted) by XCKE, PLL operation is halted by PLLC, and clock supply to USB block is halted by SCKE. To prev ent unstable behav ior by unstable clock, clock supply to USB block must be obey ed the process, that is, enables clock input by XCKE, wait until oscillation stabilized, start PLL by PLLC, wait until oscillation stabilized (less than 1ms), and start clock supply to USB block by SCKE. Remote wakeup f unction When dev ice is in suspended state, outputs remote wakeup signal and can cancel suspended state to receiv e resume f rom USB. Remote wakeup f unction is only eff ectiv e in Suspended state in which dev ice state shif ts f rom Conf igured state, so don't use to other dev ice state. Xin Xout M66290A Rf Rd C1 C2 Xin Xout M66290A clock input open (1) In case of crystal oscillation (2) In case of external clock input Figure 1. Xin and Xout connections XTAL Place the parts as near the terminal as possible |
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