M66290AFP datasheet(16/54 Pages) RENESAS

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USB DEVICE CONTROLLER

M66290AGP/FP

MITSUBISHI <DIGITAL ASSP>

Reset

Function

Name

Bit

The factor is different by the direction of the transfer of each endpoint.

In each endpoint, this bit changes to "1" when the transmission of all

stored data is completed (direction:IN) and when received the packet

which is exceeded to maximum packet size (direction:OUT).

The endpoint which occurs the interrupt can be checked to see the

EPB_EMP_OVR[5:0].

This flag is cleared to clear the status flag of EPB_EMP_OVR[5:0].

W/R

Endpoint5-0 buffer

empty/size error

interrupt

BEMP

This bit changes to "1" when the stage of control transfer is shifted.

There are five factors, that is, setup stage end, control write transfer

status stage shift, control read transfer status stage shift, control transfer

end, and control transfer sequence error.

Four factors, except for setup stage end, can be masked by the

corresponded bit of the "Interrupt Enable Register0".

If "0" is written, status flag is cleared.

If "1" is written, flag is not changed.

Control transfer

stage transition

interrupt

This bit changes to "1" when device state shifted.

There are four factors, that is, USB reset detect, suspend detect,

"Set Address" execution, and "Set Configuration" execution.

These four factors can be masked by the corresponded bit of

"Interrupt Enable Register0" .

If "0" is written, status flag is cleared.

If "1" is written, flag is not changed.

Device state

transition interrupt

This bit changes to "1" when detected SOF.

If "0" is written, status flag is cleared.

If "1" is written, flag is not changed.

SOF detect

interrupt

This bit changes to "1" when USB bus state changed("J" to "K" or "SE0")

under the condition that resume interrupt enable flag is set.

This bit is set even if the internal clock (sck) is in halt state.

If "0" is written after enabled internal clock as operation, status flag is

cleared. But if internal clock is in halt state, flag is not cleared.

If "1" is written, flag is not changed.

Resume detect

interrupt

This bit changes to "1" when Vbus input changed both "0" to "1" and

"1" to "0".

As to the Vbus input state, confirm to see the bit of Vbus input port.

This bit is set even if the internal clock (sck) is in halt state.

If "0" is written after enabled internal clock as operation, status flag is

cleared. But if internal clock is in halt state, flag is not cleared.

If "1" is written, flag is not changed.

Vbus interrupt

SOFR

CTRT

DVST

RESM

W/R

VBUS

Bit

Name

W/R

USB

S/W

H/W

BEMP

INTN

VALID

DVSQ[2:0]

CTSQ[2:0]

CTRT

Vbus

INTR

DVST

SOFR

RESM

VBUS

D10

D11

D12

D15

D13

D14

(2-5) Interrupt Status Register 0 (Address : 18h)

M66290AFP Datasheet(PDF) 16 Page - Renesas Technology Corp

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