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M66290AFP Datasheet(PDF) 37 Page - Renesas Technology Corp |
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M66290AFP Datasheet(HTML) 37 Page - Renesas Technology Corp |
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37 / 54 page ![]() USB DEVICE CONTROLLER M66290AGP/FP MITSUBISHI <DIGITAL ASSP> 36 Function Name Bit Name Bit Reset - - 0 W/R - - 0 W/R Write/Read "0" If "1" is written into this bit when the selected endpoint is set to IN, IN buffer effective state flag and the data (byte) which is written are cleared. If the IVAL="1" and BCLR="1" is written at the same time, the data is cleared but the IN buffer effective state flag is set.(This is effective to transmit 0 length data) If "1" is written into this bit when the selected endpoint is set to OUT, OUT buffer effective state flag and the read data (byte) are cleared. If it is set to double buffer, the state of buffer which can be read or write for CPU bus is cleared. To set the EPi_ACLR, USB bus buffer is cleared. This bit is not changed when "0" is written. Buffer clear If the selected endpoint is set to IN, this becomes IN buffer effective state flag. When set to "1", it becomes transmit data set state. (SIE is available to read) When the data (byte) which exceeds to the maximum packet size (MXPS) is written, this bit is set to "1". In short packet transmit, set this bit to "1" after wrote the transmit data. If IVAL="1" and BCLR="1" is written at the same time, the IN buffer effective state flag is set to "1". (This is effective to transmit 0 length data) If the selected endpoint is set to OUT, it becomes to OUT buffer effective state status. Status "1" shows that there is data which is available to read. When Creq bit is "0", the value of this bit is effective. This bit is not changed when "1" is written. Flag is not changed when "0" is written. IN buffer status 12 BCLR IVAL 13 Reserved 15, 14 W/R USB S/W H/W DMA_DTLN[10:0] Dreq BCLR IVAL D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D15 D13 D14 (4-5) DMA_FIFO Control Register (Address : 4Ah) |
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