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M66290AFP Datasheet(PDF) 18 Page - Renesas Technology Corp |
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M66290AFP Datasheet(HTML) 18 Page - Renesas Technology Corp |
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18 / 54 page ![]() USB DEVICE CONTROLLER M66290AGP/FP MITSUBISHI <DIGITAL ASSP> 17 Reset Function Name Bit Name Bit R - 00h 00h Write/Read "0" EPB_RDY [5:0] Endpoint5-0 buffer ready interrupt When buffer becomes ready (read/write enabled) to each endpoint, the bit which corresponds to the number of endpoint changes to "1". The factor of the interrupt is different by the transfer condition of each endpoint. 1. As to EP0 This bit changes to "1" when receive buffer(OUT) became ready (read enabled) in control write transfer. If it is set to control write continuous receive mode or completed receiving of the data of 255Bytes or received short data packet, this bit changes to "1". This bit is not changed even if the transmission buffer(IN) became ready (write enabled) in control read transfer. The ready state of the transmission buffer(IN) can be known by the buffer empty interrupt. 2. As to EP1 to EP5, when CPU access This bit changes to "1" when each buffer of each endpoint became ready(read/write enabled). This bit also changes to "1" when set the direction of the transfer to IN in initialization. 3. As to EP1 to EP5, when DAM access If the direction of the transfer is set to OUT, this bit changes to "1" when received short data packet and then completed DMA transfer of received data. In this case, clear is only available to write the BCLR command. This bit is not changed if the direction of transfer is set to IN. Clearance of this flag is different by the transfer direction of endpoint. 1. If the transfer direction is OUT After set the number of the object endpoint to the "FIFO Selection Register", write BCLR command or read all data of the buffer, then flag is cleared. (When DMA access, clearance is only available to write BCLR command) 2. If the direction is IN After set the number of the object endpoint to the "FIFO Selection Register", write IVAL command or write data into the buffer of maximum packet size (buffer size, if in continuous transmission mode ), then flag is cleared. Reserved 5 to 0 15 to 6 W/R USB S/W H/W EPB_RDY[5:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D15 D13 D14 (2-6) Interrupt Status Register 1 (Address : 1Ah) |
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