M66290AFP datasheet(21/54 Pages) RENESAS

21 / 54 page

USB DEVICE CONTROLLER

M66290AGP/FP

MITSUBISHI <DIGITAL ASSP>

(3) Control transfer / Enumeration

In control transf er, there are setup stage, data stage,

and status stage.

M66290A manages stage and inf orm CPU the stage

shif t by interrupt. CPU do stage transact of control

transf er according to the interrupt f actor.

Setup stage

In setup stage, 8By tes request (setup data) of setup

transaction data packet which transf erred f rom host

is stored into f our registers automatically (Request,

Value, Index, and Length register).

Except f or dev ice state shif t request (Set Address and

Set Conf iguration) which can cope with by the automatic

response control f unction, analy sis (decode) and

execution of contents of request must be done by CPU.

By executing the request, it proceeds to data stage or

to status stage.

Data stage

Data stage executes IN transaction or OUT transaction

according to the contents of request. If it is control

write transf er, data stage is OUT transaction and CPU

prepares f or data receiv e at the timing of interrupt in

setup stage and reads the receiv ed data f rom endpoint

FIFO when data receiv e ended.

USB bus connect

Full speed

dev ice recognition

Clock ON

Initializing

Tr ON

Vbus interrupt

USB reset

USB reset receive

DVST interrupt

USB request

(Control transf er)

Get xx command

CTRT interrupt

Set response data

USB request

Set Address

CTRT/DVST interrupt

(Automatic response av ailable)

USB request

Get xx command

CTRT interrupt

Set Conf iguration

CTRT/DVST interrupt

(Automatic response av ailable)

USB request

Set xx command

CTRT interrupt

Set response data

Read receiv ed data

Def ault

state

Address

state

Conf igured

state

Idle

(Powered)

If it is control read transf er, data stage is IN transaction

and CPU prepares f or data transmit (write into endpoint

FIFO) at the timing of interrupt in setup stage.

M66290A is equipped with control transf er continuous

transmit and receiv e f unction. Af ter ended data stage,

it proceeds to status stage.

M66290A

Dev ice f irmware

Dev ice state

Figure 3. Abstract of enumeration operations

Status stage

Status stage executes receiv e/transmit of N ull data

(data length 0), in both control write and control read

transf er. Receiv e/transmit of N ull data is possible to

set control transf er complete enable bit (CCPL) af ter

ended setup stage.

Control transf er complete enable bit is reset when

receiv ed setup packet.

Control transf er executes data transf er using EP0.

To both control read and control write, buff er size of

EP0 can be set by a unit of 64By tes by "Control

Transf er Control Register".

Access to EP0_FIFO data register must be done by

CPU access. DMA transf er can not be set.

Figure 3. shows the abstract of enumeration

operations.

M66290AFP Datasheet(PDF) 21 Page - Renesas Technology Corp

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