M66290AFP datasheet(12/54 Pages) RENESAS

12 / 54 page

USB DEVICE CONTROLLER

M66290AGP/FP

MITSUBISHI <DIGITAL ASSP>

Each of "Set Address" and "Set Conf iguration" execution

detects the dev ice state shif t by analy zing the dev ice

request in control transf er.

Each of these f our f actors can be set of its interrupt to

enable or disable by setting the corresponded bit of

interrupt enable register 0.

For example by using this interrupt, when USB bus reset

is detected, a step to USB bus is av ailable and when

suspend is detected, a step to shif t dev ice to low power

consumption.

Control transfer stage transition interrupt (CTRT)

M66290A manages the sequence of control transf er

by H/W.

Each stage of c ontrol transf er, such as setup stage,

data stage, and status stage can be known to ref er to

the "Interrupt Status Register 0".

Control transf er stage transition interrupt is occurred

when the control transf er stage is shif ted.

There are f iv e f actors, that is, setup stage end,

control write transf er stage shif t, control read transf er

stage shif t, control transf er end, and control transf er

sequence error.

Except f or setup stage, Each of these f our f actors can

be set of its interrupt to enable or disable by setting the

corresponded bit of interrupt enable register 0.

As to control transf er sequence error which can be

recognized by H/W, ref er to "Control transf er stage

shif t" in the item of "(3) Control transf er/enumeration"

in the latter part.

Endpoint buffer empty/size-over interrupt (BEMP)

Interrupt f actor is diff erent by transf er direction of

endpoint.

1. In case of transf er direction is IN

In each endpoint, interrupt occurs when transmission

ended of all data which is stored in the buff er.

By this interrupt, when endpoint is set to double buff er,

end of data transmission of all data of the buff er can

be known.

And also can know the end of data transmission of

control read transf er in endpoint 0 (EP0).

2. In case of transf er direction is OUT

In each endpoint, interrupt occurs in data packet

receiv e when receiv ed packet which exceeds the

maximum packet size.

By ref er to EPB_EMP_OVR[5:0] of interrupt status

interrupt.

Endpoint buffer not ready interrupt (INTN)

When the buff er is in not ready state to IN/OUT token

of each endpoint, interrupt occurs at the timing of token

packet receiv e end.

By ref er to EPB_NRDY[ 5:0] of interrupt status register 1,

it can be known which endpoint occurred the interrupt.

If endpoint is set to isochronous transf er, when ov er-run/

under-run error is occurred, interrupt occurs at the timing

of token packet receiv e end.

And if it is set to isochronous (OUT), if receiv ed data

has

error such as CRC error, interrupt occurs at the timing of

transaction end.

The v ariety of error in isochronous transf er is known to

ref er "Isochronous Status Register".

Endpoint buffer ready interrupt (INTR)

Interrupt occurs when the buff er of each endpoint

became ready (read/write is av ailable).

It can be known which endpoint occurred the interrupt

to ref er EPB_RDY [5:0] of interrupt status register 1.

According to the endpoint and its access mode, the

f actor of interrupt is diff erent as f ollows.

1. In case of EP0

Interrupt occurs when receiv e (OUT) buff er of endpoint

0 became ready.

If it is set to control write continuous receiv e mode,

when continuous receiv e of 255 by tes ended or when

receiv ed short packet, interrupt occurs.

Interrupt is not occurred ev en if the transmit buff er

became ready.

2. In case of EP1 to EP5, when CPU access

Interrupt occurs when the buff er of each endpoint

became ready.

3. In case of EP1 to EP5, when DMA access

If the transf er direction is set to OUT, interrupt occurs

when receiv ed short data packet and then ended DMA

transf er.

Interrupt is not occurred if the transf er direction is set

to IN.

M66290AFP Datasheet(PDF) 12 Page - Renesas Technology Corp

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