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SH7149 Datasheet(PDF) 35 Page - Renesas Technology Corp |
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SH7149 Datasheet(HTML) 35 Page - Renesas Technology Corp |
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35 / 1022 page  Rev. 3.00 May 17, 2007 Page xxxv of xliv Figure 19.8 State Transitions in Boot Mode............................................................................... 763 Figure 19.9 Programming/Erasing Overview Flow.................................................................... 764 Figure 19.10 RAM Map after Download.................................................................................... 765 Figure 19.11 Programming Procedure........................................................................................ 766 Figure 19.12 Erasing Procedure.................................................................................................. 771 Figure 19.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming (Overview)............................................................................................................. 773 Figure 19.14 Procedure for Programming User MAT in User Boot Mode ................................ 775 Figure 19.15 Procedure for Erasing User MAT in User Boot Mode .......................................... 777 Figure 19.16 Transitions to and from Error Protection State...................................................... 781 Figure 19.17 Emulation of Flash Memory in RAM.................................................................... 782 Figure 19.18 Example of Overlapped RAM Operation .............................................................. 783 Figure 19.19 Programming of Tuned Data ................................................................................. 784 Figure 19.20 Switching between User MAT and User Boot MAT ............................................ 786 Figure 19.21 Timing of Contention between SCO Download Request and Interrupt Request............................................................................................. 787 Figure 19.22 Flow of Processing by the Boot Program.............................................................. 792 Figure 19.23 Sequence of Bit-Rate Matching............................................................................. 793 Figure 19.24 Formats in the Communications Protocol ............................................................. 794 Figure 19.25 Sequence of New Bit Rate Selection..................................................................... 806 Figure 19.26 Sequence of Programming .................................................................................... 810 Figure 19.27 Sequence of Erasure ..............................................................................................814 Section 20 Masked ROM Figure 20.1 Masked ROM Block Diagram................................................................................. 831 Section 21 RAM Figure 21.1 On-chip RAM Addresses ........................................................................................ 833 Section 24 Electrical Characteristics Figure 24.1 EXTAL Clock Input Timing ................................................................................... 898 Figure 24.2 CK Clock Output Timing ........................................................................................ 899 Figure 24.3 Power-On Oscillation Settling Timing .................................................................... 899 Figure 24.4 Oscillation Settling Timing on Return from Standby (Return by Reset)................. 899 Figure 24.5 Oscillation Settling Timing on Return from Standby (Return by NMI or IRQ)...... 900 Figure 24.6 Reset Input Timing.................................................................................................. 902 Figure 24.7 Interrupt Signal Input Timing.................................................................................. 902 Figure 24.8 Interrupt Signal Output Timing ............................................................................... 903 Figure 24.9 Bus Release Timing................................................................................................. 903 Figure 24.10 Pin Driving Timing in Standby Mode ................................................................... 903 Figure 24.11 Basic Bus Timing for Normal Space (No Wait).................................................... 905 Figure 24.12 Basic Bus Timing for Normal Space (One Software Wait Cycle) ........................ 906 |
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