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SH7149 Datasheet(PDF) 47 Page - Renesas Technology Corp |
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SH7149 Datasheet(HTML) 47 Page - Renesas Technology Corp |
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47 / 1022 page ![]() Section 1 Overview Rev. 3.00 May 17, 2007 Page 3 of 974 REJ09B0229-0300 Items Specification On-chip ROM • 256 kbytes On-chip RAM • 8 kbytes Bus state controller (BSC) • Address space: A maximum 64 Mbytes for each of two areas (CS0 and CS1) (only in SH7149) • 8-bit external bus (only in SH7149) • 16-bit external bus (only in SH7149) • The following features settable for each area independently Bus size (8 or 16 bits) Number of access wait cycles Idle wait cycle insertion Supports SRAM • Outputs a chip select signal according to the target area Data transfer controller (DTC) (only in F-ZTAT version) • Data transfer activated by an on-chip peripheral module interrupt can be done independently of the CPU transfer. • Transfer mode selectable for each interrupt source (transfer mode is specified in memory) • Multiple data transfer enabled for one activation source • Various transfer modes Normal mode, repeat mode, or block transfer mode can be selected. • Data transfer size can be specified as byte, word, or longword • The interrupt that activated the DTC can be issued to the CPU. A CPU interrupt can be requested after one data transfer completion. • A CPU interrupt can be requested after all specified data transfer completion. Interrupt controller (INTC) • Five external interrupt pins (NMI and IRQ3 to IRQ0) • On-chip peripheral interrupts: Priority level set for each module • Vector addresses: A vector address for each interrupt source User debugging interface (H-UDI) (only in F-ZTAT version) • E10A emulator support Advanced user debugger (AUD) (only in F-ZTAT version supporting full functions of E10A) • E10A emulator support |
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