SH7149 datasheet(27/1022 Pages) RENESAS

27 / 1022 page

Rev. 3.00 May 17, 2007 Page xxvii of xliv

Section 9 Bus State Controller (BSC)

Figure 9.1 Block Diagram of BSC.............................................................................................. 198

Figure 9.2 Normal Space Basic Access Timing (Access Wait 0)............................................... 216

Figure 9.3 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access,

WM Bit in CSnWCR = 0 (Access Wait = 0, Cycle Wait = 0)................................... 217

Figure 9.4 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access,

WM Bit in CSnWCR = 1 (Access Wait = 0, Cycle Wait = 0)................................... 218

Figure 9.5 Example of 16-Bit Data-Width SRAM Connection.................................................. 219

Figure 9.6 Example of 8-Bit Data-Width SRAM Connection.................................................... 219

Figure 9.7 Wait Timing for Normal Space Access (Software Wait Only) ................................. 220

Figure 9.8 Wait State Timing for Normal Space Access

(Wait State Insertion Using

WAIT Signal)................................................................221

Figure 9.9

CSn Assert Period Extension.....................................................................................222

Figure 9.10 Bus Arbitration when DTC Activation Request Occur

during External Space Access from CPU ................................................................ 227

Figure 9.11 Bus Arbitration Timing ........................................................................................... 229

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Figure 10.1 Block Diagram of MTU2 ........................................................................................ 238

Figure 10.2 Complementary PWM Mode Output Level Example ............................................. 305

Figure 10.3 PWM Output Level Setting Procedure in Buffer Operation.................................... 310

Figure 10.4 Example of Counter Operation Setting Procedure .................................................. 323

Figure 10.5 Free-Running Counter Operation ............................................................................ 324

Figure 10.6 Periodic Counter Operation..................................................................................... 325

Figure 10.7 Example of Setting Procedure for Waveform Output by Compare Match.............. 325

Figure 10.8 Example of 0 Output/1 Output Operation ............................................................... 326

Figure 10.9 Example of Toggle Output Operation ..................................................................... 326

Figure 10.10 Example of Input Capture Operation Setting Procedure ....................................... 327

Figure 10.11 Example of Input Capture Operation..................................................................... 328

Figure 10.12 Example of Synchronous Operation Setting Procedure ........................................ 329

Figure 10.13 Example of Synchronous Operation...................................................................... 330

Figure 10.14 Compare Match Buffer Operation......................................................................... 331

Figure 10.15 Input Capture Buffer Operation............................................................................. 332

Figure 10.16 Example of Buffer Operation Setting Procedure................................................... 332

Figure 10.17 Example of Buffer Operation (1)........................................................................... 333

Figure 10.18 Example of Buffer Operation (2)........................................................................... 334

Figure 10.19 Example of Buffer Operation When TCNT_0 Clearing is Selected

for TGRC_0 to TGRA_0 Transfer Timing............................................................ 335

Figure 10.20 Cascaded Operation Setting Procedure ................................................................. 336

Figure 10.21 Cascaded Operation Example (a) .......................................................................... 337

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