SH7149 datasheet(12/1022 Pages) RENESAS

12 / 1022 page

Rev. 3.00 May 17, 2007 Page xii of xliv

Section 7 User Break Controller (UBC)............................................................ 119

7.1

Features.............................................................................................................................. 119

7.2

Input/Output Pins...............................................................................................................121

7.3

Register Descriptions ......................................................................................................... 122

7.3.1

Break Address Register A (BARA) ...................................................................... 123

7.3.2

Break Address Mask Register A (BAMRA)......................................................... 123

7.3.3

Break Bus Cycle Register A (BBRA)................................................................... 124

7.3.4

Break Data Register A (BDRA) (F-ZTAT Version Only).................................... 126

7.3.5

Break Data Mask Register A (BDMRA) (F-ZTAT Version Only) ...................... 127

7.3.6

Break Address Register B (BARB) ...................................................................... 128

7.3.7

Break Address Mask Register B (BAMRB) ......................................................... 129

7.3.8

Break Data Register B (BDRB) (F-ZTAT Version Only) .................................... 130

7.3.9

Break Data Mask Register B (BDMRB) (F-ZTAT Version Only)....................... 131

7.3.10 Break Bus Cycle Register B (BBRB) ................................................................... 132

7.3.11 Break Control Register (BRCR) ........................................................................... 134

7.3.12 Execution Times Break Register (BETR) (F-ZTAT Version Only)..................... 139

7.3.13 Branch Source Register (BRSR) (F-ZTAT Version Only)................................... 140

7.3.14 Branch Destination Register (BRDR) (F-ZTAT Version Only) ........................... 141

7.4

Operation ........................................................................................................................... 142

7.4.1

Flow of the User Break Operation ........................................................................ 142

7.4.2

User Break on Instruction Fetch Cycle ................................................................. 143

7.4.3

User Break on Data Access Cycle ........................................................................ 144

7.4.4

Sequential Break ................................................................................................... 145

7.4.5

Value of Saved Program Counter ......................................................................... 145

7.4.6

PC Trace ............................................................................................................... 146

7.4.7

Usage Examples.................................................................................................... 147

7.5

Usage Notes ....................................................................................................................... 152

Section 8 Data Transfer Controller (DTC) ........................................................ 155

8.1

Features.............................................................................................................................. 155

8.2

Register Descriptions ......................................................................................................... 157

8.2.1

DTC Mode Register A (MRA) ............................................................................. 158

8.2.2

DTC Mode Register B (MRB).............................................................................. 159

8.2.3

DTC Source Address Register (SAR)................................................................... 161

8.2.4

DTC Destination Address Register (DAR)........................................................... 161

8.2.5

DTC Transfer Count Register A (CRA) ............................................................... 162

8.2.6

DTC Transfer Count Register B (CRB)................................................................ 163

8.2.7

DTC Enable Registers A to E (DTCERA to DTCERE) ....................................... 164

8.2.8

DTC Control Register (DTCCR) .......................................................................... 165

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