SH7149 datasheet(20/1022 Pages) RENESAS

20 / 1022 page

Rev. 3.00 May 17, 2007 Page xx of xliv

17.2

Usage Notes ....................................................................................................................... 705

Section 18 I/O Ports........................................................................................... 707

18.1

Port A................................................................................................................................. 708

18.1.1 Register Descriptions............................................................................................ 710

18.1.2 Port A Data Register L (PADRL) ......................................................................... 710

18.1.3 Port A Port Register L (PAPRL) .......................................................................... 712

18.2

Port B ................................................................................................................................. 713

18.2.1 Register Descriptions............................................................................................ 714

18.2.2 Port B Data Registers H and L (PBDRH and PBDRL) ........................................ 714

18.2.3 Port B Port Registers H and L (PBPRH and PBPRL) .......................................... 717

18.3

Port D (SH7149 Only) ....................................................................................................... 719

18.3.1 Register Descriptions............................................................................................ 720

18.3.2 Port D Data Register L (PDDRL) ......................................................................... 720

18.3.3 Port D Port Register L (PDPRL) .......................................................................... 722

18.4

Port E ................................................................................................................................. 723

18.4.1 Register Descriptions............................................................................................ 725

18.4.2 Port E Data Registers H and L (PEDRH and PEDRL) ......................................... 725

18.4.3 Port E Port Registers H and L (PEPRH and PEPRL) ........................................... 728

18.5

Port F ................................................................................................................................. 730

18.5.1 Register Descriptions............................................................................................ 731

18.5.2 Port F Data Register L (PFDRL) .......................................................................... 731

Section 19 Flash Memory.................................................................................. 733

19.1

Features.............................................................................................................................. 733

19.2

Overview............................................................................................................................ 735

19.2.1 Block Diagram...................................................................................................... 735

19.2.2 Operating Mode .................................................................................................... 736

19.2.3 Mode Comparison ................................................................................................ 738

19.2.4 Flash Memory Configuration................................................................................ 739

19.2.5 Block Division ...................................................................................................... 740

19.2.6 Programming/Erasing Interface ............................................................................ 740

19.3

Input/Output Pins...............................................................................................................743

19.4

Register Descriptions ......................................................................................................... 743

19.4.1 Registers ............................................................................................................... 743

19.4.2 Programming/Erasing Interface Registers ............................................................ 746

19.4.3 Programming/Erasing Interface Parameters ......................................................... 753

19.4.4 RAM Emulation Register (RAMER).................................................................... 768

19.5

On-Board Programming Mode .......................................................................................... 770

19.5.1 Boot Mode ............................................................................................................ 770

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