SH7149 datasheet(42/1022 Pages) RENESAS

42 / 1022 page

Rev. 3.00 May 17, 2007 Page xlii of xliv

Table 17.7

SH7149 Multiplexed Pins (Port E) ....................................................................... 633

Table 17.8

Multiplexed Pins (Port F) ..................................................................................... 634

Table 17.9

SH7146 Pin Functions in Each Operating Mode .................................................. 635

Table 17.10

SH7149 Pin Functions in Each Operating Mode (1) ........................................ 638

Table 17.11

SH7149 Pin Functions in Each Operating Mode (2) ........................................ 642

Table 17.12

Table 17.13

Transmit Forms of Input Functions Allocated to Multiple Pins ....................... 695

Section 18 I/O Ports

Table 18.1

Table 18.2

Port A Data Register L (PADRL) Read/Write Operations ................................... 701

Table 18.3

Table 18.4

Port B Data Register (PBDR) Read/Write Operations ......................................... 706

Table 18.5

Table 18.6

Port D Data Register L (PDDRL) Read/Write Operations ................................... 711

Table 18.7

Table 18.8

Port E Data Register (PEDR) Read/Write Operations.......................................... 718

Table 18.9

Table 18.10

Port F Data Register L (PFDRL) Read/Write Operations................................. 722

Section 19 Flash Memory

Table 19.1

(1) Relationship between FWE and MD Pins and Operating Modes

(SH7146) .............................................................................................................. 727

Table 19.1

(2) Relationship between FWE and MD Pins and Operating Modes

(SH7149) .............................................................................................................. 727

Table 19.2

Comparison of Programming Modes.................................................................... 728

Table 19.3

Pin Configuration.................................................................................................. 733

Table 19.4

(1) Register Configuration .................................................................................... 734

Table 19.4

(2) Parameter Configuration ................................................................................. 734

Table 19.5

Table 19.6

Usable Parameters and Target Modes................................................................... 744

Table 19.7

Overlapping of RAM Area and User MAT Area.................................................. 759

Table 19.8

Peripheral Clock (P

φ) Frequency that Can Automatically Adjust Bit Rate

of This LSI............................................................................................................ 761

Table 19.9

Hardware Protection ............................................................................................. 779

Table 19.10

Software Protection........................................................................................... 780

Table 19.11

Initiation Intervals of User Branch Processing ................................................. 789

Table 19.12

Initial User Branch Processing Time ................................................................ 789

Table 19.13

Inquiry and Selection Commands..................................................................... 795

Table 19.14

Programming and Erasure Commands ............................................................. 809

Table 19.15

Status Codes...................................................................................................... 820

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