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SH7149 Datasheet(PDF) 31 Page - Renesas Technology Corp |
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SH7149 Datasheet(HTML) 31 Page - Renesas Technology Corp |
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31 / 1022 page  Rev. 3.00 May 17, 2007 Page xxxi of xliv Figure 10.99 Input Capture Input Signal Timing........................................................................ 420 Figure 10.100 Counter Clear Timing (Compare Match) (Channels 0 to 4) ................................ 421 Figure 10.101 Counter Clear Timing (Compare Match) (Channel 5)......................................... 421 Figure 10.102 Counter Clear Timing (Input Capture) (Channels 0 to 5).................................... 422 Figure 10.103 Buffer Operation Timing (Compare Match)........................................................ 422 Figure 10.104 Buffer Operation Timing (Input Capture) ........................................................... 422 Figure 10.105 Buffer Transfer Timing (when TCNT Cleared) .................................................. 423 Figure 10.106 Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop) ... 423 Figure 10.107 Transfer Timing from Buffer Register to Temporary Register (TCNTS Operating)............................................................................................. 424 Figure 10.108 Transfer Timing from Temporary Register to Compare Register ....................... 424 Figure 10.109 TGI Interrupt Timing (Compare Match) (Channels 0 to 4)................................. 425 Figure 10.110 TGI Interrupt Timing (Compare Match) (Channel 5) ......................................... 425 Figure 10.111 TGI Interrupt Timing (Input Capture) (Channels 0 to 4)..................................... 426 Figure 10.112 TGI Interrupt Timing (Input Capture) (Channel 5) ............................................. 426 Figure 10.113 TCIV Interrupt Setting Timing............................................................................ 427 Figure 10.114 TCIU Interrupt Setting Timing............................................................................ 427 Figure 10.115 Timing for Status Flag Clearing by CPU (Channels 0 to 4) ................................ 428 Figure 10.116 Timing for Status Flag Clearing by CPU (Channel 5)......................................... 428 Figure 10.117 Timing for Status Flag Clearing by DTC Activation (Channels 0 to 4) .............. 429 Figure 10.118 Timing for Status Flag Clearing by DTC Activation (Channel 5)....................... 429 Figure 10.119 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .............. 430 Figure 10.120 Contention between TCNT Write and Clear Operations..................................... 431 Figure 10.121 Contention between TCNT Write and Increment Operations ............................. 432 Figure 10.122 Contention between TGR Write and Compare Match......................................... 433 Figure 10.123 Contention between Buffer Register Write and Compare Match ........................ 434 Figure 10.124 Contention between Buffer Register Write and TCNT Clear.............................. 435 Figure 10.125 Contention between TGR Read and Input Capture (Channels 0 to 4)................. 436 Figure 10.126 Contention between TGR Read and Input Capture (Channel 5) ......................... 436 Figure 10.127 Contention between TGR Write and Input Capture (Channels 0 to 4)................ 437 Figure 10.128 Contention between TGR Write and Input Capture (Channel 5)......................... 437 Figure 10.129 Contention between Buffer Register Write and Input Capture............................ 438 Figure 10.130 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection .................................................................................... 439 Figure 10.131 Counter Value during Complementary PWM Mode Stop................................... 440 Figure 10.132 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode...................................................................... 441 Figure 10.133 Reset Synchronous PWM Mode Overflow Flag ................................................. 442 Figure 10.134 Contention between Overflow and Counter Clearing.......................................... 443 Figure 10.135 Contention between TCNT Write and Overflow................................................. 444 |
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