SH7149 datasheet(29/1022 Pages) RENESAS

29 / 1022 page

Rev. 3.00 May 17, 2007 Page xxix of xliv

Figure 10.56 Timing for Synchronous Counter Clearing ........................................................... 377

Figure 10.57 Example of Procedure for Setting Output Waveform Control at Synchronous

Counter Clearing in Complementary PWM Mode ................................................ 378

Figure 10.58 Example of Synchronous Clearing in Dead Time during Up-Counting

(Timing (3) in Figure 10.56; Bit WRE of TWCR in MTU2 is 1).......................... 379

Figure 10.59 Example of Synchronous Clearing in Interval Tb at Crest

(Timing (6) in Figure 10.56; Bit WRE of TWCR in MTU2 is 1).......................... 380

Figure 10.60 Example of Synchronous Clearing in Dead Time during Down-Counting

(Timing (8) in Figure 10.56; Bit WRE of TWCR is 1).......................................... 381

Figure 10.61 Example of Synchronous Clearing in Interval Tb at Trough

(Timing (11) in Figure 10.56; Bit WRE of TWCR is 1)........................................ 382

Figure 10.62 MTU2–MTU2S Synchronous Clearing-Suppressed Interval Specified

by SCC Bit in TWCR ............................................................................................ 383

Figure 10.63 Example of Procedure for Suppressing MTU2–MTU2S

Synchronous Counter Clearing.............................................................................. 384

Figure 10.64 Example of Synchronous Clearing in Dead Time during Up-Counting

(Timing (3) in Figure 10.56; Bit WRE is 1 and Bit SCC is 1

in TWCR of MTU2S)............................................................................................ 385

Figure 10.65 Example of Synchronous Clearing in Interval Tb at Crest

(Timing (6) in Figure 10.56; Bit WRE is 1 and Bit SCC is 1

in TWCR of MTU2S)............................................................................................ 386

Figure 10.66 Example of Synchronous Clearing in Dead Time during Down-Counting

(Timing (8) in Figure 10.56; Bit WRE is 1 and Bit SCC is 1

in TWCR of MTU2S)............................................................................................ 387

Figure 10.67 Example of Synchronous Clearing in Interval Tb at Trough

(Timing (11) in Figure 10.56; Bit WRE is 1 and Bit SCC is 1

in TWCR of MTU2S)............................................................................................ 388

Figure 10.68 Example of Counter Clearing Operation by TGRA_3 Compare Match................ 389

Figure 10.69 Example of Output Phase Switching by External Input (1)................................... 390

Figure 10.70 Example of Output Phase Switching by External Input (2)................................... 391

Figure 10.71 Example of Output Phase Switching

by Means of UF, VF, WF Bit Settings (1)............................................................. 391

Figure 10.72 Example of Output Phase Switching

by Means of UF, VF, WF Bit Settings (2)............................................................. 392

Figure 10.73 Example of Interrupt Skipping Operation Setting Procedure................................ 393

Figure 10.74 Periods during which Interrupt Skipping Count can be Changed.......................... 394

Figure 10.75 Example of Interrupt Skipping Operation ............................................................. 394

Figure 10.76 Example of Operation when Buffer Transfer is Suppressed

(BTE1 = 0 and BTE0 = 1) ..................................................................................... 396

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