SH7261 datasheet(859/1348 Pages) RENESAS

859 / 1348 page

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 827 of 1312

REJ09B0320-0200

Bit 3 — Reserved. The written value should always be '0' and the returned value is '0'.

Bit 2 — Message Transmission Priority (MCR2): MCR2 selects the order of transmission for

pending transmit data. If this bit is set, pending transmit data are sent in order of the bit position in

the Transmission Pending Register (TXPR). The order of transmission starts from Mailbox-15 as

the highest priority, and then down to Mailbox-1 (if those mailboxes are configured for

transmission).

If MCR2 is cleared, all messages for transmission are queued with respect to their priority (by

running internal arbitration). The highest priority message has the Arbitration Field (STDID + IDE

bit + EXTID (if IDE = 1) + RTR bit) with the lowest digital value and is transmitted first. The

internal arbitration includes the RTR bit and the IDE bit (internal arbitration works in the same

way as the arbitration on the CAN Bus between two CAN nodes starting transmission at the same

time).

This bit can be modified only in Reset or Halt mode.

Bit 2: MCR2

Description

Transmission order determined by message identifier priority (Initial value)

Transmission order determined by mailbox number priority (Mailbox-15

→

Mailbox-1)

Bit 1—Halt Request (MCR1): Setting the MCR1 bit causes the CAN controller to complete its

current operation and then enter Halt mode (where it is cut off from the CAN bus). The RCAN-ET

remains in Halt Mode until the MCR1 is cleared. During the Halt mode, the CAN Interface does

not join the CAN bus activity and does not store messages or transmit messages. All the user

registers (including Mailbox contents and TEC/REC) remain unchanged with the exception of

IRR0 and GSR4 which are used to notify the halt status itself. If the CAN bus is in idle or

intermission state regardless of MCR6, RCAN-ET will enter Halt Mode within one Bit Time. If

MCR6 is set, a halt request during Bus Off will be also processed within one Bit Time. Otherwise

the full Bus Off recovery sequence will be performed beforehand. Entering the Halt Mode can be

notified by IRR0 and GSR4.

If both MCR14 and MCR6 are set, MCR1 is automatically set as soon as RCAN-ET enters

BusOff.

In the Halt mode, the RCAN-ET configuration can be modified with the exception of the Bit

Timing setting, as it does not join the bus activity. MCR[1] has to be cleared by writing a '0' in

order to re-join the CAN bus. After this bit has been cleared, RCAN-ET waits until it detects 11

recessive bits, and then joins the CAN bus.

SH7261 Datasheet(PDF) 859 Page - Renesas Technology Corp