SH7672 datasheet(365/1292 Pages) RENESAS

365 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 339 of 1262

REJ09B0437-0100

8.4.5

Number of Bus Cycles and DREQ Pin Sampling Timing

(1) Number of Bus Cycles

When the DMAC is the bus master, the number of bus cycles is controlled by the bus state

controller (BSC) in the same way as when the CPU is the bus master. For details, see section 7,

Bus State Controller (BSC).

(2) DREQ Pin Sampling Timing

Figures 8.13 to 8.16 show the DREQ input sampling timings in each bus mode.

CKIO

DREQ

DACK

Bus cycle

(Rising)

(Active-high)

1st acceptance

2nd acceptance

CPU

Acceptance start

DMAC

Non sensitive period

Figure 8.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection

CKIO

DREQ

(Overrun 0 at

high level)

DACK

(Active-high)

Bus cycle

1st acceptance

CPU

DMAC

CKIO

DREQ

(Overrun 1 at

high level)

DACK

(Active-high)

Bus cycle

2nd acceptance

CPU

DMAC

Acceptance

start

Acceptance

start

2nd acceptance

1st acceptance

Non sensitive period

Figure 8.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection

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