SH7672 datasheet(369/1292 Pages) RENESAS

369 / 1292 page

Section 9 Clock Pulse Generator (CPG)

Rev. 1.00 Nov. 14, 2007 Page 343 of 1262

REJ09B0437-0100

Section 9 Clock Pulse Generator (CPG)

This LSI has a clock pulse generator (CPG) that generates an internal clock (I

φ), a peripheral clock

φ), and a bus clock (Bφ). The CPG consists of a crystal oscillator, PLL circuits, and divider

circuits.

9.1

Features

• Four clock operating modes

The mode can be selected from among the four clock operating modes based on the frequency

range to be used and the input clock type: the crystal resonator, the external clock, the crystal

resonator for USB, or the external clock for USB.

• Three clocks generated independently

An internal clock (I

φ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip

peripheral modules; a bus clock (B

φ = CKIO) for the external bus interface

• Frequency change function

Internal and peripheral clock frequencies can be changed independently using the PLL (phase

locked loop) circuits and divider circuits within the CPG. Frequencies are changed by software

using frequency control register (FRQCR) settings.

• Power-down mode control

The clock can be stopped in sleep mode and software standby mode, and specific modules can

be stopped using the module standby function. For details on clock control in the power-down

modes, see section 11, Power-Down Modes.

SH7672 Datasheet(PDF) 369 Page - Renesas Technology Corp