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SH7672 Datasheet(PDF) 372 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 372 Page - Renesas Technology Corp |
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372 / 1292 page  Section 9 Clock Pulse Generator (CPG) Rev. 1.00 Nov. 14, 2007 Page 346 of 1262 REJ09B0437-0100 (6) Standby Control Circuit The standby control circuit controls the states of the clock pulse generator and other modules during clock switching, or sleep or software standby mode. In addition, the standby control register is provided to control the power-down mode of other modules. For details on the standby control register, see section 11, Power-Down Modes. (7) Frequency Control Register (FRQCR) The frequency control register (FRQCR) has control bits assigned for the following functions: clock output/non-output from the CKIO pin during software standby mode, the frequency multiplication ratio of PLL circuit, and the frequency division ratio of the internal clock and the peripheral clock (P φ). |
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