SH7672 datasheet(376/1292 Pages) RENESAS

376 / 1292 page

Section 9 Clock Pulse Generator (CPG)

Rev. 1.00 Nov. 14, 2007 Page 350 of 1262

REJ09B0437-0100

• Mode 2

In mode 2, the CKIO pin functions as an input pin and draws an external clock signal. The

PLL circuit shapes waveform and the frequency is multiplied according to the frequency

control register setting before the clock is supplied to the LSI. The frequency range of CKIO is

from 60 to 100 MHz*. To reduce current supply, pull up the EXTAL pin and open the XTAL

pin when the LSI is used in mode 2. When USB is not used, pull up the USB_X1 pin and open

the USB_X2 pin.

Note: * These are target values that were set when this hardware manual was prepared. The

guaranteed maximum frequencies will be determined after the final evaluation result of

this LSI is obtained.

• Mode 3

In mode 3, clock is input from the USB_X1 pin or the crystal oscillator. The external clock is

input through this pin and waveform is shaped in the PLL circuit. Then the frequency is

multiplied according to the frequency control register setting before the clock is supplied to the

LSI. The frequency of CKIO is the same as that of the input clock 96 MHz*. To reduce current

supply, pull up the EXTAL pin and open the XTAL pin when the LSI is used in mode 3. When

the USB crystal resonator is not used, open the USB_X2 pin.

Note: * These are target values that were set when this hardware manual was prepared. The

guaranteed maximum frequencies will be determined after the final evaluation result of

this LSI is obtained.

SH7672 Datasheet(PDF) 376 Page - Renesas Technology Corp