SH7672 datasheet(367/1292 Pages) RENESAS

Part #	SH7672

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

PDF	1292 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 341 of 1262

REJ09B0437-0100

Figure 8.17 shows the TEND output timing.

CKIO

DACK

DREQ

TEND

Bus cycle

End of DMA transfer

DMAC

CPU

DMAC

Figure 8.17 Example of DMA Transfer End Signal Timing

(Cycle Steal Mode Level Detection)

The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is

performed for an 8-bit, 16-bit, or 32-bit external device, when longword access is performed for an

8-bit or 16-bit external device, or when word access is performed for an 8-bit external device.

When a setting is made so that the DMA transfer size is divided into multiple bus cycles and the

CS signal is negated between bus cycles, note that DACK and TEND are divided like the CS

signal for data alignment as shown in figure 8.18. Figures 8.13 to 8.17 show cases in which TACK

and TEND are not divided at the time of DMA transfer.

SH7672 Datasheet(PDF) 367 Page - Renesas Technology Corp