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SH7672 Datasheet(PDF) 405 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 405 Page - Renesas Technology Corp |
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405 / 1292 page ![]() Section 11 Power-Down Modes Rev. 1.00 Nov. 14, 2007 Page 379 of 1262 REJ09B0437-0100 Bit Bit Name Initial Value R/W Description 4 MSTP7 0 R/W Module Stop 7 When the MSTP7 bit is set to 1, the clock supply to the FPU is halted. After the MSTP7 bit is set to 1, the value of 0 cannot be written for clearing. In other words, once the MSTP7 bit is set to 1 and the clock supply to the FPU is temporarily halted, then the clock supply to the FPU cannot be restarted by clearing the MSTP7 bit to 0. If the clock supply to the FPU is halted and then restarted, a power-on reset must be performed for this LSI. 0: FPUC runs. 1: Clock supply to FPU halted. 3 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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