SH7672 datasheet(429/1292 Pages) RENESAS

429 / 1292 page

Section 12 Ethernet Controller (EtherC)

Rev. 1.00 Nov. 14, 2007 Page 403 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Description

PRM

R/W

Promiscuous Mode

Setting this bit enables all Ethernet frames to be

received. All Ethernet frames means all receivable

frames, irrespective of differences or enabled/disabled

status (destination address, broadcast address,

multicast bit, etc.).

0: EtherC performs normal operation

1: EtherC performs promiscuous mode operation

12.3.2

EtherC Status Register (ECSR)

ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can

be notified to the CPU by interrupts. When 1 is written to the PSRTO, LCHNG, MPD, and ICD,

the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that generate

interrupt, the interrupt can be enabled or disabled according to the corresponding bit in ECSIPR.

The interrupts generated due to this status register are indicated in the ECI bit in EESR.

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

RRRRRRRRRRR

R/W

----------------

-----------

PSRTO

LCHNG

MPD

ICD

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