SH7672 datasheet(430/1292 Pages) RENESAS

430 / 1292 page

Section 12 Ethernet Controller (EtherC)

Rev. 1.00 Nov. 14, 2007 Page 404 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Description

31 to 5



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

PSRTO

R/W

PAUSE Frame Retransfer Retry Over

Indicates that during the retransfer of PAUSE frames

when the flow control is enabled, the number of retries

has exceeded the upper limit set in the automatic

PAUSE frame retransfer count set register

(TPAUSER).

0: Number of PAUSE frame retransfers has not

exceeded the upper limit

1: Number of PAUSE frame retransfers has exceeded

the upper limit



Reserved

This bit is always read as 0. The write value should

always be 0.

LCHNG

R/W

Link Signal Change

Indicates that the LNKSTA signal input from the PHY

has changed from high to low or low to high.

To check the current Link state, refer to the LMON bit

in the PHY status register (PSR).

0: Changes in the LNKSTA signal are not detected

1: Changes in the LNKSTA signal are detected (high

to low or low to high)

MPD

R/W

Magic Packet Detection

Indicates that a Magic Packet has been detected on

the line.

0: Magic Packet has not been detected

1: Magic Packet has been detected

ICD

R/W

Illegal Carrier Detection

Indicates that the PHY has detected an illegal carrier

on the line. If a change in the signal input from the

PHY occurs before the software recognition period,

the correct information may not be obtained. Refer to

the timing specification for the PHY used.

0: LSI has not detected an illegal carrier on the line

1: LSI has detected an illegal carrier on the line

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