SH7672 datasheet(431/1292 Pages) RENESAS

431 / 1292 page

Section 12 Ethernet Controller (EtherC)

Rev. 1.00 Nov. 14, 2007 Page 405 of 1262

REJ09B0437-0100

12.3.3

EtherC Interrupt Permission Register (ECSIPR)

ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources

indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

RRRRRRRRRRR

R/W

----------------

-----------

PSRTO

LCHNG

MPD

ICD

Bit

Bit Name

Initial

Value

R/W

Description

31 to 5



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

PSRTOIP

R/W

PAUSE Frame Retransfer Retry Over Interrupt Enable

0: Interrupt notification by the PSRTO bit is disabled

1: Interrupt notification by the PSRTO bit is enabled

—

Reserved

This bit is always read as 0. The write value should

always be 0.

LCHNGIP

R/W

LINK Signal Changed Interrupt Enable

0: Interrupt notification by the LCHNG bit is disabled

1: Interrupt notification by the LCHNG bit is enabled

MPDIP

R/W

Magic Packet Detection Interrupt Enable

0: Interrupt notification by the MPD bit is disabled

1: Interrupt notification by the MPD bit is enabled

ICDIP

R/W

Illegal Carrier Detection Interrupt Enable

0: Interrupt notification by the ICD bit is disabled

1: Interrupt notification by the ICD bit is enabled

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