SH7672 datasheet(231/1292 Pages) RENESAS

231 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 205 of 1262

REJ09B0437-0100

7.4.4

SDRAM Control Register (SDCR)

SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be

connected.

Bit:

Initial Value:

R/W:

Bit:

Initial Value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

R/W





A3ROW[1:0]

A3COL[1:0]







DEEP



RFSH RMODEPDOWN BACTV





Bit

Bit Name

Initial

Value

R/W

Description

31 to 14



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DEEP

R/W

Deep Power-Down Mode

This bit is valid for low-power SDRAM. If the RFSH or

RMODE bit is set to 1 while this bit is set to 1, the deep

power-down entry command is issued and the low-

power SDRAM enters the deep power-down mode.

0: Self-refresh mode

1: Deep power-down mode



Reserved

This bit is always read as 0. The write value should

always be 0.

RFSH

R/W

Refresh Control

Specifies whether or not the refresh operation of the

SDRAM is performed.

0: No refresh

1: Refresh

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