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SH7672 Datasheet(PDF) 232 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 232 Page - Renesas Technology Corp |
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232 / 1292 page ![]() Section 7 Bus State Controller (BSC) Rev. 1.00 Nov. 14, 2007 Page 206 of 1262 REJ09B0437-0100 Bit Bit Name Initial Value R/W Description 10 RMODE 0 R/W Refresh Control Specifies whether to perform auto-refresh or self- refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refresh starts immediately. When the RFSH bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in registers RTCSR, RTCNT, and RTCOR. 0: Auto-refresh is performed 1: Self-refresh is performed 9 PDOWN 0 R/W Power-Down Mode Specifies whether the SDRAM will enter the power- down mode after the access to the SDRAM. With this bit being set to 1, after the SDRAM is accessed, the CKE signal is driven low and the SDRAM enters the power-down mode. 0: The SDRAM does not enter the power-down mode after being accessed. 1: The SDRAM enters the power-down mode after being accessed. 8 BACTV 0 R/W Bank Active Mode Specifies to access whether in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands). 0: Auto-precharge mode (using READA and WRITA commands) 1: Bank active mode (using READ and WRIT commands) 7 to 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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