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ADS1282IPW Datasheet(PDF) 4 Page - Texas Instruments

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Part # ADS1282IPW
Description  High-Resolution Analog-to-Digital Converter
PDF  52 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS1282IPW Datasheet(HTML) 4 Page - Texas Instruments

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ADS1282
SBAS418E – SEPTEMBER 2007 – REVISED OCTOBER 2008 ........................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V,
VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, High-Resolution Mode, and fDATA = 1000SPS, unless otherwise noted.
ADS1282
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DC PERFORMANCE (continued)
PGA = 1
2
ppm/°C
Gain drift
PGA = 16
9
ppm/°C
Gain matching(9)
0.3
0.8
%
Common-mode rejection
fCM = 60Hz
(10)
95
110
dB
AVDD, AVSS
80
90
Power-supply rejection
fPS = 60Hz
(10)
dB
DVDD
90
115
VOLTAGE REFERENCE INPUTS
(AVDD – AVSS)
Reference input voltage
(VREF = VREFP – VREFN)
0.5
5
V
+ 0.2
Negative reference input
VREFN
AVSS – 0.1
VREFP – 0.5
V
Positive reference input
VREFP
VREFN + 0.5
AVDD + 0.1
V
High-resolution mode
85
k
Ω
Reference input impedance
Low-power mode
170
k
Ω
DIGITAL FILTER RESPONSE
Passband ripple
±0.003
dB
Passband (–0.01dB)
0.375 × fDATA
Hz
Bandwidth (–3dB)
0.413 × fDATA
Hz
High-pass filter corner
0.1
10
Hz
Stop band attenuation(11)
135
dB
Stop band
0.500 × fDATA
Hz
Minimum phase filter
5/fDATA
Group delay
s
Linear phase filter
31/fDATA
Minimum phase filter
10/fDATA
Settling time (latency)
s
Linear phase filter
62/fDATA
DIGITAL INPUT/OUTPUT
VIH
0.8 × DVDD
DVDD
V
VIL
DGND
0.2 × DVDD
V
VOH
IOH = 1mA
0.8 × DVDD
V
VOL
IOL = 1mA
0.2 × DVDD
V
Input leakage
0 < VDIGITAL IN < DVDD
±10
µA
Clock input
fCLK
1
4.096
MHz
Serial clock rate
fSCLK
fCLK/2
MHz
(9)
Gain match relative to PGA = 1.
(10) fCM is the input common-mode frequency. fPS is the power-supply frequency.
(11) Input frequencies in the range of NfCLK/512 ± fDATA/2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency
ranges intermodulation = 120dB, typ.
4
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1282



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