ADS1282IPW datasheet(43/52 Pages) TI

43 / 52 page

RESET

CLKInput

RESET

DOUT

DIN

SCLK

SYNC

MFLAG

DGND

CLK

4,12,23

SYNC

MFLAG1

DRDY

MFLAG2

DVDD

47W

1 F

+3.3V

(1)

ADS1282

RESET

DOUT

DIN

SCLK

SYNC

MFLAG

DGND

CLK

6,12,25

DVDD

47W

DRDY

47W

1 F

+3.3V

(1)

ADS1282

4.096MHzClock

FPGA

BYPAS

1 F

BYPAS

1 F

DOUT1

DIN1

SCLK1

47W

DOUT2

DIN2

SCLK2

ADS1282

www.ti.com ........................................................................................................................................ SBAS418E – SEPTEMBER 2007 – REVISED OCTOBER 2008

Figure 71 shows the digital connection to a field

For best performance, the FPGA and the ADS1282s

programmable gate array (FPGA) device. In this

should operate from the same clock. Avoid ringing on

example, two ADS1282s are shown connected. The

the digital inputs. 47

Ω resistors in series with the

DRDY output from each ADS1282 can be used;

digital traces can help to reduce ringing by controlling

however, when the devices are synchronized, the

impedances. Place the resistors at the source (driver)

DRDY output from only one device is sufficient. A

end of the trace. Unused digital inputs should not

shared SCLK line between the devices is optional.

float; tie them to DVDD or GND. This includes the

modulator data pins, M0, M1, and MCLK.

The modulator over-range flag (MFLAG) from each

device ties to the FPGA. For synchronization, one

SYNC control line connects all ADS1282 devices.

The RESET line also connects to all ADS1282

devices.

NOTE: Dashed line is optional.

(1) For DVDD < 2.25V, see the DVDD Power Supply section.

Figure 71. Microcontroller Interface with Dual ADS1282s

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ADS1282IPW Datasheet(PDF) 43 Page - Texas Instruments

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