ADS1282IPW datasheet(19/52 Pages) TI

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AVSS

300mV<(VREFPorVREFN)<AVDD+300mV

Sinc Filter Stage (sinx/x)

DIGITAL FILTER

H(Z)=

N(1

)

-1

(7)

SincFilter

(Decimateby

8to128)

CoefficientFilter

(FIR)

(Decimateby32)

High-PassFilter

(IIR)

Filter

MUX

ToOutputRegister

FromModulator

DirectModulator

BitStream

CAL

Block

Code

Clip

FilterMode

(RegisterSelect)

ADS1282

www.ti.com ........................................................................................................................................ SBAS418E – SEPTEMBER 2007 – REVISED OCTOBER 2008

Table 4. Digital Filter Selection

The ADS1282 reference inputs are protected by ESD

diodes. In order to prevent these diodes from turning

FILTR[1:0] BITS

DIGITAL FILTERS SELECTED

on, the voltage on either input must stay within the

Bypass; modulator output mode

range shown in Equation 6:

Sinc

Sinc + FIR

Sinc + FIR + HPF

(6)

(low-pass and high-pass)

Note that the minimum valid input for VREFN is

AVSS – 0.1V and maximum valid input for VREFP is

AVDD + 0.1V.

The sinc filter is a variable decimation rate, fifth-order,

low-pass filter. Data are supplied to this section of the

A high-quality +5V reference voltage is necessary for

filter from the modulator at the rate of fMOD (fCLK/4).

achieving the best performance from the ADS1282.

The sinc filter attenuates the high-frequency noise of

Noise and drift on the reference degrade overall

the modulator, then decimates the data stream into

system performance, and it is critical that special care

parallel data. The decimation rate affects the overall

be given to the circuitry generating the reference

data rate of the converter; it is set by the DR[2:0]

voltages in order to achieve full performance. See the

Application

Information

section

for

reference

recommendations.

Equation 7 shows the scaled Z-domain transfer

function of the sinc filter.

The digital filter receives the modulator output and

decimates the data stream. By adjusting the amount

of filtering, tradeoffs can be made between resolution

and data rate: filter more for higher resolution, filter

less for higher data rate.

Where:

The digital filter is comprised of three cascaded filter

N = decimation ratio

stages: a variable-decimation, fifth-order sinc filter; a

fixed-decimation

FIR,

low-pass

filter

(LPF)

with

Table 5. Sinc Filter Data Rates (CLK = 4.096MHz)

selectable phase; and a programmable, first-order,

DECIMATION

SINC DATA RATE

high-pass filter (HPF), as shown in Figure 42.

DR[2:0] REGISTER

RATIO (N)

(SPS)

The output can be taken from one of the three filter

000

128

8,000

blocks, as Figure 42 shows. To implement the digital

001

16,000

filter completely off-chip, select the filter bypass

010

32,000

setting (modulator output). For partial filtering by the

011

64,000

ADS1282, select the sinc filter output. For complete

on-chip filtering, activate both the sinc and FIR

100

128,000

stages. The HPF can then be included to remove dc

and low frequencies from the data. Table 4 shows the

filter options.

Figure 42. Digital Filter and Output Code Processing

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