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38K2 Datasheet(PDF) 253 Page - Renesas Technology Corp |
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38K2 Datasheet(HTML) 253 Page - Renesas Technology Corp |
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253 / 358 page ![]() 2.14 Flash memory Rev.2.00 Oct 15, 2006 page 104 of 112 38K2 Group REJ09B0338-0200 APPLICATION Fig. 2.14.3 Structure of Flash memory control register Fig. 2.14.2 Memory map of registers related to flash memory 2.14.3 Related registers Flash memory control register (FMCR) 0FFE16 Address Flash memory control register b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register (FMCR : address 0FFE16) (Note 1) b 0 1 2 4 Name Functions At reset R W 0 0 0 User area/Boot area selection bit (Note 4) CPU rewrite mode select bit (Note 2) 0 : Busy (being written or erased) 1 : Ready 5 6 7 0 Undefined Undefined Undefined RY/BY status flag 3 0: User ROM area 1: Boot ROM area Flash memory reset bit (Note 3) 0: Normal operation 1: Reset CPU rewrite mode entry flag 0: Normal mode 1: CPU rewrite mode 0 : Normal mode (Software commands invalid) 1 : CPU rewrite mode (Software commands acceptable) 1 Nothing is arranged for these bits. If writing, set “0”. When these bits are read out, the contents are undefined. Notes 1: The contents of flash memory control register are “XXX00001” just after reset release. 2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not this procedure, this bit will not be set to “1”. Additionally, it is required to ensure that no interrupt will be generated during that interval. Use the control program in the area except the built-in flash memory for write to this bit. 3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after setting bit 3 to “1”. 4: Use the control program in the area except the built-in flash memory for write to this bit. |
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