38K2 datasheet(290/358 Pages) RENESAS

290 / 358 page

3.2 Notes on use

Rev.2.00

Oct 15, 2006

page 29 of 99

38K2 Group

REJ09B0338-0200

APPENDIX

3.2.13 Notes on programming

(1)

Processor status register

➀ Initializing of processor status register

Flags which affect program execution must be initialized after a reset.

In particular, it is essential to initialize the T and D flags because they have an important effect

on calculations.

q Reason

After a reset, the contents of the processor status register (PS) are undefined except for the I

flag which is “1”.

Fig. 3.2.4 Initialization of processor status register

➁ How to reference the processor status register

To reference the contents of the processor status register (PS), execute the PHP instruction once

then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its

original status.

A NOP instruction should be executed after every PLP instruction.

Fig. 3.2.6 Stack memory contents after PHP

instruction execution

Fig. 3.2.5 Sequence of PLP instruction execution

Reset

↓

Initializing of flags

↓

Main program

PLP instruction execution

↓

NOP

(S)

(S)+1

Stored PS

(2)

BRK instruction

➀ Interrupt priority level

When the BRK instruction is executed with the following conditions satisfied, the interrupt execution

is started from the address of interrupt vector which has the highest priority.

• Interrupt request bit and interrupt enable bit are set to “1”.

• Interrupt disable flag (I) is set to “1” to disable interrupt.

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