38K2 datasheet(288/358 Pages) RENESAS

288 / 358 page

3.2 Notes on use

Rev.2.00

Oct 15, 2006

page 27 of 99

38K2 Group

REJ09B0338-0200

APPENDIX

3.2.7 Notes on A/D converter

(1)

Analog input pin

Make the signal source impedance for analog input low, or equip an analog input pin with an external

capacitor of 0.01

µF to 1 µF. Further, be sure to verify the operation of application products on the

user side.

q Reason

An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when

signals from signal source with high impedance are input to an analog input pin, charge and

discharge noise generates. This may cause the A/D conversion precision to be worse.

(2)

Clock frequency during A/D conversion

The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock

frequency is too low. Thus, make sure the following during an A/D conversion.

• f(XIN) is 500 kHz or more

• Do not execute the STP instruction

3.2.8 Notes on watchdog timer

qMake sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog

timer keeps counting during that term.

qWhen the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program

____________

3.2.9 Notes on RESET pin

Connecting capacitor

In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the

RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When

connecting the capacitor, note the following :

• Make the length of the wiring which is connected to a capacitor as short as possible.

• Be sure to verify the operation of application products on the user side.

q Reason

If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may

cause a microcomputer failure.

3.2.10 Notes on PLL

q6 MHZ or 12 MHZ external oscillator can be connected as an input reference clock (f(XIN)). When using

the frequency synthesized clock function, we recommend using the fastest frequency possible of f(XIN)

as an input clock reference for the PLL.

qWhen enabling PLL operation from PLL disabled status (disabled when reset), set the USB clock select

bit of USBCON to “0” (f(XIN)) to operate with the main clock (f(XIN)).

qWhen supplying fVCO to the USB block after setting PLL operation enable bit to “1” (PLL enabled), wait

for the oscillation stable time (1 ms or less) of PLL to avoid any instability caused by the clock, then set

USB clock select bit to “1” (USB clock).

qWhen selecting fSYN as an internal system clock, fUSB must be 48 MHz.

qWhen selecting fSYN as an internal system clock, change the system clock selection bit to main clock

(f(XIN)) before executing STP instruction. It is because the following are needed for the low-power consumption:

•fUSB must be stopped by disabling PLL operation in Stop mode.

•The taimer 1 for waiting oscillation stabilization when returning from Stop mode will require the input

count source.

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