38K2 datasheet(310/358 Pages) RENESAS

310 / 358 page

3.4 List of registers

Rev.2.00

Oct 15, 2006

page 49 of 99

38K2 Group

REJ09B0338-0200

APPENDIX

Fig. 3.4.30 Structure of EP00 control register 3

Control transfer completion

enable bit

Not used

CTENDE00

b7:b1

–

EP00 control register 3 (EP00CON3) [address 001C16]

0 : NAK transmission in the status stage

1 : Control transfer completion enabled (SIE transmits

NULL/ACK.) (valid in PID00 = “012”)

At reception of SETUP token:

This bit is cleared to “0” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

Bit name

Bit symbol

At reset

Function

H/W

S/W

Fig. 3.4.29 Structure of EP11 control register 2

Fig. 3.4.28 Structure of EP10 control register 2

Buffer enable bit

Not used

BVAL10

b7:b1

–

EP10 control register 2 (EP10CON2) [address 001B16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

0 : NAK transmission (SIE is disabled to read a buffer.)

1 : Transmitting/receiving data set state (SIE is possible to

read from/write to a buffer.) (Valid in PID10 = “012”)

At reception of SETUP token:

This bit is cleared to “0” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

B0VAL11

b7:b1

–

EP11 control register 2 (EP11CON2) [address 001B16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

–: State remaining

Buffer 0 status bit

Not used

This bit set to “1” shows the transmitting data is in a set

state (SIE is possible to read).

Write “0” when writing.

“0” is read when reading.

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