38K2 datasheet(306/358 Pages) RENESAS

306 / 358 page

3.4 List of registers

Rev.2.00

Oct 15, 2006

page 45 of 99

38K2 Group

REJ09B0338-0200

APPENDIX

Fig. 3.4.18 Structure of EP00 control register 1

Response PID bit

Not used

PID00 [1:0]

b7:b2

–

EP00 control register 1 (EP00CON1) [address 001A16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

b1 b0

0 0 : NAK

0 1 : Automatic response (ACK, NAK, DATA0, DATA1)

1 X : STALL

At occurrence of control transfer error:

B1 is set to “1” by the hardware.

At reception of SETUP token:

B1 and b0 are cleared to “0” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

000

Fig. 3.4.17 Structure of EP11 set register

Fig. 3.4.16 Structure of EP10 stage register

SETUP packet detection bit

Not used

SETUP10

b7:b1

–

EP10 stage register (EP10STG) [address 001916]

Bit name

Bit symbol

At reset

Function

H/W

S/W

This bit is set to “1” at reception of SETUP packet.

Writing “0” clears this bit if the next SETUP token does

not occur.

Writing “1” causes no state change of the status flags.

This bit change is not for an interrupt source.

Write “0” when writing.

“0” is read when reading.

–: State remaining

000

Not used

Sequence toggle bit clear bit

Not used

Transfer direction bit

Not used

Transfer type bite

b2:b0

SQCL11

DIR11

TYP11

EP11 set register (EP11CFG) [address 001916]

–

Bit name

Bit symbol

At reset

Function

H/W

S/W

Write “0” when writing.

“0” is read when reading.

0 : Toggle bit clear disabled

1 : Writing “1” clears the toggle bit and DATA0 is used

as the next data PID.

“0” is always read when reading.

Write “0” when writing.

“0” is read when reading.

0 : IN transfer disabled

1 : IN (Data is transmitted to the host.)

Write “0” when writing.

“0” is read when reading.

0 : Transfer disabled

1 : Interrupt transfer

–: State remaining

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