38K2 datasheet(304/358 Pages) RENESAS

304 / 358 page

3.4 List of registers

Rev.2.00

Oct 15, 2006

page 43 of 99

38K2 Group

REJ09B0338-0200

APPENDIX

Fig. 3.4.12 Structure of EP00 stage register

SETUP packet detection bit

Not used

SETUP00

b7:b1

–

EP00 stage register (EP00STG) [address 001916]

Bit name

Bit symbol

At reset

Function

H/W

S/W

This bit is set to “1” at reception of SETUP packet.

Writing “0” to this bit clears this bit if the next SETUP

token does not occur.

Writing “1” to this bit causes no state change of the

status flags.

Write “0” when writing.

“0” is read when reading.

–: State remaining

000

Fig. 3.4.13 Structure of EP01 set register

Double buffer beginning address set

bit

Buffer mode select bit

Sequence toggle bit clear bit

Interrupt toggle mode select bit

Transfer direction bit

Transfer type bite

BSIZ01

[1:0]

DBLB01

SQCL01

ITMD01

DIR01

TYP01

[1:0]

–

EP01 set register (EP01CFG) [address 001916]

Bit name

Bit symbol

At reset

Function

H/W

S/W

In double buffer mode set the beginning address of

buffer 1 area, using a relative value for the beginning

address of buffer 0.

b1b0

0 0 = 8 bytes

0 1 = 16 bytes

1 0 = 64 bytes

1 1 = 128 bytes

0 : Single buffer mode

1 : Double buffer mode

0 : Toggle bit clear disabled

1 : Writing “1” clears the toggle bit and DATA0 is used

as the next data PID.

“0” is always read when reading.

0 : Normal mode

1 : Continuous toggle mode (valid at Interrupt IN transfer)

0 : OUT (Data is received from the host.)

1 : IN (Data is transmitted to the host.)

b7b6

0 0 : Transfer disabled

0 1 : Bulk transfer

1 0 : Interrupt transfer

1 1 : Isochronous transfer

–: State remaining

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