38K2 datasheet(308/358 Pages) RENESAS

308 / 358 page

3.4 List of registers

Rev.2.00

Oct 15, 2006

page 47 of 99

38K2 Group

REJ09B0338-0200

APPENDIX

Fig. 3.4.24 Structure of EP00 control register 2

Buffer enable bit

Not used

BVAL00

b7:b1

–

EP00 control register 2 (EP00CON2) [address 001B16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

0 : NAK transmission (SIE is disabled to read a buffer.)

1 : Transmitting/receiving data set state (SIE is possible

to read from/write to a buffer.)

At reception of SETUP token:

This bit is cleared to “0” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

Fig. 3.4.22 Structure of EP10 control register 1

Fig. 3.4.23 Structure of EP11 control register 1

Response PID bit

Not used

PID10 [1:0]

b7:b2

–

EP10 control register 1 (EP10CON1) [address 001A16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

b1 b0

0 0 : NAK

0 1 : Automatic response (ACK, NAK, DATA0, DATA1)

1 X : STALL

At occurrence of control transfer error:

B1 is set to “1” by the hardware.

At reception of SETUP token:

B1 and b0 are cleared to “0” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

000

Response PID bit

Not used

PID11

[1:0]

b7:b2

–

EP11 control register 1 (EP11CON1) [address 001A16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

b1 b0

0 0 : NAK

0 1 : Automatic response (NAK, DATA0, DATA1)

1 X : STALL

Write “0” when writing.

“0” is read when reading.

–: State remaining

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