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38K2 Datasheet(PDF) 325 Page - Renesas Technology Corp

Part # 38K2
Description  RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
PDF  358 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

38K2 Datasheet(HTML) 325 Page - Renesas Technology Corp

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3.4 List of registers
Rev.2.00
Oct 15, 2006
page 64 of 99
38K2 Group
REJ09B0338-0200
APPENDIX
b7
b0
DSCONN1
DSPTEN1
DSSUSP1
DSDETE1
DSRSTO1
DSRSMO1
DSRMOD1
DSLSPD1
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
DP1 control register (DP1CON) [address 002C16]
Bit name
Bit symbol
At reset
Function
H/W
S/W
Downstream port 1 connect bit
Downstream port 1 enable bit
Downstream port 1 suspend bit
Downstream port 1 connect-
state detection enable bit
Downstream port 1 SE0 signal
transmit bit
Downstream port 1 resume
signal transmit bit
Downstream port 1 bus-state
read mode control bit
Downstream port 1 USB transfer
0 : Disconnect ; PTCON1 interrupt enabled
1 : Connect ; PTDIS1 interrupt enabled
0 : Downstream port 1 disabled
1 : Downstream port 1 enabled ; This bit is cleared when
an interrupt of PTDIS1 or PTERR1 is generated.
0 : No port suspended
1 : Port suspended; This bit is cleared when an interrupt
of PTDIS1 or PTRSM1 is generated.
0 : Connect/disconnect-state detection disabled ; PTCON1
and PTDIS1 interrupts disabled
1 : Connect/disconnect-state detection enabled ; This bit
is cleared when an interrupt of PTCON1, PTDIS1 or
PTERR1 is generated.
0 : Being not output
1 : SE0 signal being output
0 : Being not output
1 : K-signal being output ; When writing “0”, a low-speed
EOP is output and then a transition to being not
output occurs.
0 : Mode where a downstream port 1 bus-state is read,
using RD signal
1 : Mode where a downstream port 1 bus-state is read,
using EOF2 signal (internal signal)
0 : Full-speed mode (12MHz)
1 : Low-speed mode (1.5 MHz)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
–: State remaining
W
R
b7
b0
DSCONN2
DSPTEN2
DSSUSP2
DSDETE2
DSRSTO2
DSRSMO2
DSRMOD2
DSLSPD2
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
DP2 control register (DP2CON) [address 002C16]
Bit name
Bit symbol
At reset
Function
H/W
S/W
Downstream port 2 connect bit
Downstream port 2 enable bit
Downstream port 2 suspend bit
Downstream port 2 connect-
state detection enable bit
Downstream port 2 SE0 signal
transmit bit
Downstream port 2 resume
signal transmit bit
Downstream port 2 bus-state
read mode control bit
Downstream port 2 USB transfer
speed select bit
0 : Disconnect ; PTCON2 interrupt enabled
1 : Connect ; PTDIS2 interrupt enabled
0 : Downstream port 2 disabled
1 : Downstream port 2 enabled ; This bit is cleared when
an interrupt of PTDIS2 or PTERR2 is generated.
0 : No port suspended
1 : Port suspended; This bit is cleared when an interrupt
of PTDIS2 or PTRSM2 is generated.
0 : Connect-state detection disabled ; PTCON2 and PTDIS2
interrupts disabled
1 : Connect-state detection enabled ; This bit is cleared when an
interrupt of PTCON2, PTDIS2 or PTERR2 is generated.
0 : Being not output
1 : SE0 signal being output
0 : Being not output
1 : K-signal being output ; When writing “0”, a low-speed
EOP is output and then a transition to being not
output occurs.
0 : Mode where a downstream port 2 bus-state is read,
using RD signal
1 : Mode where a downstream port 2 bus-state is read,
using EOF2 signal (internal signal)
0 : Full-speed mode (12MHz)
1 : Low-speed mode (1.5 MHz)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
–: State remaining
W
R
Fig. 3.4.61 Structure of DP1 control register
Fig. 3.4.62 Structure of DP2 control register



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