38K2 datasheet(326/358 Pages) RENESAS

326 / 358 page

3.4 List of registers

Rev.2.00

Oct 15, 2006

page 65 of 99

38K2 Group

REJ09B0338-0200

APPENDIX

CPU channel receive enable bit

CPU channel transmit enable bit

Memory channel operation

enable bit

Not used

RXB_ENB

TXB_ENB

MC_ENB

b7:b3

–

EXB interrupt source enable register (EXBICON) [address 003016]

(Note)

000

Bit name

Bit symbol

At reset

Function

H/W

S/W

0 : Operation disabled (Interrupt disabled)

1 : Operation enabled (Receive buffer full interrupt enabled)

0 : Operation disabled (Interrupt disabled)

1 : Operation enabled (Transmit buffer empty interrupt enabled)

0 : Operation disabled (Memory channel operation end

interrupt disabled)

1 : Operation enabled (Memory channel operation end

interrupt disabled)

Write “0” when writing.

“0” is read when reading.

–: State remaining

Note: Do not set each bit simultaneously.

Fig. 3.4.65 Structure of EXB interrupt source enable register

Fig. 3.4.63 Structure of DP1 status register

D1MINUS

D1PLUS

b7:b2

DP1 status register (DP1STS) [address 002D16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

–: State remaining

D1- signal bit

D1+ signal bit

Not used

In-

definite

In-

definite

–

In-

definite

In-

definite

–

In DSRMOD1 = “0”, a downstream port 1 bus-state is

read, using RD signal.

In DSRMOD1 = “1”, a downstream port 1 bus-state is

read, using EOF2 signal (internal signal).

In DSRMOD1 = “0”, a downstream port 1 bus-state is

read, using RD signal.

In DSRMOD1 = “1”, a downstream port 1 bus-state is

read, using EOF2 signal (internal signal).

Write “0” when writing.

“0” is read when reading.

D2MINUS

D2PLUS

b7:b2

DP2 status register (DP2STS) [address 002D16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

–: State remaining

D2- signal bit

D2+ signal bit

Not used

In-

definite

In-

definite

–

In-

definite

In-

definite

–

In DSRMOD2 = “0”, a downstream port 2 bus-state is

read, using RD signal.

In DSRMOD2 = “1”, a downstream port 2 bus-state is

read, using EOF2 signal (internal signal).

In DSRMOD2 = “0”, a downstream port 2 bus-state is

read, using RD signal.

In DSRMOD2 = “1”, a downstream port 2 bus-state is

read, using EOF2 signal (internal signal).

Write “0” when writing.

“0” is read when reading.

Fig. 3.4.64 Structure of DP2 status register

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