H83065 datasheet(126/963 Pages) RENESAS

126 / 963 page

Section 5 Interrupt Controller

Rev. 4.00 Jan 26, 2006 page 104 of 938

REJ09B0276-0400

5.2.5

IRQ Sense Control Register (ISCR)

ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the

inputs at pins

IRQ

5 to IRQ0.

Bit

Initial value

Read/Write



R/W

These bits select level sensing or falling-edge

sensing for IRQ to IRQ interrupts



R/W

IRQ5SC

R/W

IRQ4SC

R/W

IRQ3SC

R/W

IRQ2SC

R/W

IRQ1SC

R/W

IRQ0SC

R/W

IRQ to IRQ sense control

Reserved bits

ISCR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 and 6—Reserved: These bits can be written and read, but they do not select level or

falling-edge sensing.

Bits 5 to 0—IRQ

5 to IRQ0 Sense Control (IRQ5SC to IRQ0SC): These bits select whether

interrupts IRQ

5 to IRQ0 are requested by level sensing of pins IRQ5 to IRQ0, or by falling-edge

sensing.

Bits 5 to 0

IRQ5SC to IRQ0SC Description

Interrupts are requested when

IRQ

5 to IRQ0 inputs are low

(Initial value)

Interrupts are requested by falling-edge input at

IRQ

5 to IRQ0

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